lan9218i Standard Microsystems Corp., lan9218i Datasheet
lan9218i
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lan9218i Summary of contents
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... Supports Slave-DMA — Interrupt Pin with Programmable Hold-off timer Reduces system cost and increases design flexibility SRAM-like interface easily interfaces to most embedded CPU’s or SoC’s SMSC LAN9218i LAN9218i Reduced Power Modes — Numerous power management modes — Wake on LAN* — ...
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... LAN9218i-MT FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... MAC Address Auto-Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.8.2 EEPROM Host Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.3 Internal PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.10 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.10.1 Power-On Reset (POR 3.10.2 Hardware Reset Input (nRESET 3.10.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.10.4 Soft Reset (SRST 3.10.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.11 TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SMSC LAN9218i 3 DATASHEET Revision 2.3 (08-06-08) ...
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... RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2.2 TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 System Control and Status Registers 5.3.1 ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.2 IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.3 INT_STS—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 4 DATASHEET Datasheet SMSC LAN9218i ...
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... Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.5.13 PHY Special Control/Status 112 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.1 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 113 6.1.2 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2 PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3 PIO Burst Reads 117 SMSC LAN9218i 5 DATASHEET Revision 2.3 (08-06-08) ...
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... Power Consumption (Device and System Components 126 7.5 Worst Case Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.1 100-TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 6 DATASHEET Datasheet SMSC LAN9218i ...
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... Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 6.5 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 6.6 TX Data FIFO Direct PIO Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 6.7 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 8.1 100 Pin TQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SMSC LAN9218i 7 DATASHEET Revision 2.3 (08-06-08) ...
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... Table 5.5 Backpressure Duration Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 5.6 MAC CSR Register Map Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 5.8 LAN9218i PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 6.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 6 ...
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... The LAN9218i also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9218i can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions ...
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... Compatibility with First-generation LAN9118 Family Devices The LAN9218i is driver-, register-, and footprint-compatible with previous generation LAN9118 Family devices. Drivers written for these products will work with the LAN9218i. However, in order to support HP Auto-MDIX, other components such as the magnetics and the passive components around the magnetics need to change, and supporting these changes does require a minor PCB change. A reference design for the LAN9218i will be available on SMSC’ ...
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... PIO interface function. On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port internal to the LAN9218i. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. ...
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... Serial EEPROM Interface A serial EEPROM interface is included in the LAN9218i. The serial EEPROM is optional and can be programmed with the LAN9218i MAC address. The LAN9218i can optionally load the MAC address automatically after power-on reset, hardware reset, or soft reset. ...
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... SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are supported. The LAN9218i host bus interface supports 32-bit and 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9218i can be interfaced to either Big-Endian or Little-Endian processors. ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support SMSC LAN9218i 100 PIN TQFP Figure 2.1 Pin Configuration (Top View) 14 DATASHEET Datasheet 50 D10 49 D11 48 VDD_IO 47 GND_IO 46 D12 45 D13 44 D14 43 D15 42 VDD_IO 41 GND_IO 40 D16 39 D17 38 D18 37 D19 36 D20 35 VDD_IO 34 GND_IO 33 D21 32 D22 31 D23 30 D24 29 D25 28 VDD_IO 27 GND_IO 26 D26 SMSC LAN9218i ...
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... LAN9218i when reduced power state Active low signal used to qualify read and write operations. This signal qualified with nWR is also used to wakeup the LAN9218i when reduced power state. O8/OD8 1 Programmable Interrupt request. Programmable polarity, source and buffer types. ...
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... GPO signal RX_DV/RX_CLK monitor, the EECS pin is deasserted never unintentionally access the serial EEPROM. This signal cannot function as a general-purpose input. Note: 16 DATASHEET Datasheet DESCRIPTION When the EEPROM interface is not used, the EECLK pin must be left unconnected. SMSC LAN9218i ...
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... If nRESET is left unconnected, the LAN9218i will rely on its internal power-on reset circuitry. Note: O8/OD8 1 When programmed to do so, is asserted when the LAN9218i detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note Enables Auto-MDIX ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9218i detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then ...
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... VDD_PLL PLL Ground VSS_PLL Reference Power VDD_REF Reference Ground VSS_REF Note 2.1 Please refer to the SMSC application note AN14.10 - “Migrating from LAN9118 to the LAN9218I” for additional details. SMSC LAN9218i BUFFER NUM TYPE PINS P 1 +1.8V Power from the internal PLL regulator. This pin must be connected to a 10uF capacitor (< ...
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... IRQ VDD_IO 73 AMDIX_EN D11 74 SPEED_SEL D10 DATASHEET Datasheet PIN NUM PIN NAME 76 FIFO_SEL 77 VSS_A 78 TPO- 79 TPO+ 80 VSS_A 81 VDD_A 82 TPI- 83 TPI VDD_A 86 VSS_A 87 EXRES1 88 VSS_A 89 VDD_A nRD 93 nWR 94 nCS 95 nRESET 96 GND_IO 97 VDD_IO 98 GPIO0/nLED1 99 GPIO1/nLED2 100 GPIO2/nLED3 SMSC LAN9218i ...
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... Open-drain output with 8mA sink OD8 Output 8mA symmetrical drive O8 50uA (typical) internal pull-up PU 50uA (typical) internal pull-down PD Analog input AI Analog output AO Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK SMSC LAN9218i Table 2.7 Buffer Types DESCRIPTION 21 DATASHEET Revision 2.3 (08-06-08) ...
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... Generation of control frames Interface to the internal PHY. The transmit and receive data paths are separate within the LAN9218i from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.2 Flow Control The LAN9218i Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The pause operation inhibits data transmission of data frames for a specified period of time. A Pause ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9218i address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Filtering Modes" ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9218i Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9218i packet filter function performs an imperfect address filtering against the hash table ...
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... The Diagram shown in up frame filter register’s structure. Note 3.1 Wake-up frame detection can be performed when the LAN9218i is in the power states. In the D0 state, wake-up frame detection is enabled when the WUEN bit is set. Note 3.2 Wake-up frame detection, as well as Magic Packet detection, is always enabled and cannot be disabled when the device enters the D1 state ...
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... Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. SMSC LAN9218i Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask ...
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... MAC examines receive data for a Magic Packet. The LAN9218i can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set ...
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... It should be noted that Magic Packet detection can be performed when LAN9218i is in the power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state ...
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... Whenever the LAN9218i transmits data from the Transmit Data FIFO to the network, the low order word is always transmitted first, and when the LAN9218i receives data from the network to the Receive Data FIFO, the low-order word is always received first. ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet The LAN9218i EEPROM controller also allows the host system to read, write and erase the contents of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support EEPROM Read Idle Write Data Register Write Command Register Read Command Register Section 5.3.23, "E2P_CMD – EEPROM Command Register," DATASHEET Datasheet Idle Write Command Register Read Command Register Busy Bit = 0 Read Data Register SMSC LAN9218i ...
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... ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) SMSC LAN9218i Figure 3.3 EEPROM ERASE Cycle Figure 3 ...
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... Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Figure 3.5 EEPROM EWDS Cycle Figure 3.6 EEPROM EWEN Cycle 34 DATASHEET Datasheet t CSL t CSL SMSC LAN9218i ...
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... E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Table 3.8, "Required EECLK each EEPROM operation. SMSC LAN9218i Figure 3.7 EEPROM READ Cycle Figure 3 ...
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... EEPROM Timing Refer to Section 6.9, "EEPROM Timing," on page 123 3.9 Power Management The LAN9218i supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.9.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power Management States,” on page 38. All configuration data is saved when in either of the two low power states ...
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... In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_CTRL register can be read to determine which LAN9218i device is driving the PME signal. When the LAN9218i power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the LAN9218i to the D0 state. Components,” on page 126 page 126, shows the power consumption values for each power state ...
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... A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9218i to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9218i can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Note 3.11 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.12 After a POR, nRESET or SRST, the LAN9218i will automatically check for the presence of an external EEPROM. After any of these resets the application must verify that the EPC ...
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... Resume Reset Timing After issuing a write to the BYTE_TEST register to wake the LAN9218i from a power-down state, the READY bit in PMT_CTRL will assert (set High) within 2ms. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If the software driver polls this bit and it is not set within 100ms, then an error condition occurred ...
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... When a packet is split into multiple buffers, each successive buffer may begin on any arbitrary byte. The LAN9218i can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9218i is operating in a system that always performs multi-word bursts ...
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... TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32- bit values that are used by the LAN9218i in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure ...
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... Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Optional Pad DWORDn Last Figure 3.12 TX Buffer Format Format", shows the TX Buffer written into the LAN9218i. It should be for a detailed explanation on calculating the 44 DATASHEET Datasheet 0 Section 3.11.5, SMSC LAN9218i ...
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... This value, along with the Buffer End Alignment field, is read and checked by the LAN9218i and used to determine how many extra DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9218i of the cumulative buffer sizes for a given packet. ...
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... The final buffer of any transmit packet can be any length Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Table 3.12 TX Command 'B' Format DESCRIPTION Table 3.13, "TX DATA Start Table 3.13 TX DATA Start Offset 11 10 D[31:24] D[23:16] 46 DATASHEET Datasheet Offset", shows the 01 00 D[15:8] D[7:0] SMSC LAN9218i ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9218i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION 48 DATASHEET Datasheet SMSC LAN9218i ...
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... Buffer End Alignment = 1 Data Start Offset = 10 First Segment = 0 Last Segment = 1 Buffer Size = 17 TX Com m and 'B' Packet Length = 111 SMSC LAN9218i illustrates the TX command structure for this example, and also shows 0 TX Command 'A' Data Passed to the TX Command 'B' 7-Byte Data Start Offset 79-Byte Payload ...
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... TX command structure for this example, and also shows 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3.14 TX Example 2 50 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 183-Byte Payload Data NOTE: Extra bytes between buffers are not transmitted SMSC LAN9218i ...
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... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9218i can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9218i is operating in a system that always performs multi-DWORD bursts ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support init Idle RX Interrupt Read RX Status DWORD Not Last Packet Read RX Packet init Read RX_FIFO_ INf Valid Status DWORD Read RX Status DWORD Not Last Packet Read RX Packet 52 DATASHEET Datasheet SMSC LAN9218i ...
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... FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9218i receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Figure 3.17 assumed that the host has previously read the associated 31 Optional offset DWORD0 . . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD Optional Pad DWORD0 . . Optional Pad DWORDn Figure 3.17 RX Packet Format DESCRIPTION 54 DATASHEET Datasheet 0 SMSC LAN9218i ...
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... If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN9218i DESCRIPTION 55 DATASHEET Revision 2.3 (08-06-08) ...
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... MII by 4 bits Encoder 125 Mbps Serial MLT-3 Tx MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 56 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Table 4.1. Each 4-bit data-nibble SMSC LAN9218i ...
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... INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV 00010 V INVALID, RX_ER if during RX_DV 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER if during RX_DV SMSC LAN9218i Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 0110 0111 1000 ...
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... The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 58 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID SMSC LAN9218i ...
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... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN9218i 100M PLL 25MHz 4B/5B ...
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... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 60 DATASHEET Datasheet SMSC LAN9218i ...
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... Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. SMSC LAN9218i 61 DATASHEET Revision 2.3 (08-06-08) ...
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... Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 62 DATASHEET Datasheet SMSC LAN9218i ...
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... Parallel Detection If the LAN9218i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
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... Mbps Note 4.1 The LAN9218i 10/100 PHY internal CRS signal operates in two modes: Active and Low. When in Active mode, the internal CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, the internal CRS stays low and does not indicate carrier detection ...
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... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9218i is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct cable connection vs. Cross-over cable connection. ...
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... Chapter 5 Register Description The following section describes all LAN9218i registers and data ports. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h 3Ch 24h 20h 1Ch 04h Base + 00h Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support ...
Page 67
... LAN9218i registers accordingly. 5.2 RX and TX FIFO Ports The LAN9218i contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs. 5.2.1 RX FIFO Ports The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data ...
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... Automatic Flow Control Configuration EEPROM Command EEPROM Data Reserved for future use 68 DATASHEET Datasheet DEFAULT See Page 69. 00000000h 00000000h 00000000h - 87654321h 48000000h 00000000h 00000000h 00050000h 00000000h 00000000h 00001200h 00000000h 00000000h 0000FFFFh 0000FFFFh - 00000000h - 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h - SMSC LAN9218i ...
Page 69
... IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ output is disabled and permanently deasserted. This bit has no effect on any internal interrupt status bits. 7-5 Reserved SMSC LAN9218i 50h Size: DESCRIPTION 54h Size: DESCRIPTION ...
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... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION 70 DATASHEET Datasheet TYPE DEFAULT R/W 0 NASR RO - R/W 0 NASR SMSC LAN9218i ...
Page 71
... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9218i. The LAN9218i will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 72
... GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION 72 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN9218i ...
Page 73
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2-0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN9218i 5Ch Size: DESCRIPTION 73 DATASHEET 32 bits TYPE DEFAULT R ...
Page 74
... When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 64h Size: DESCRIPTION 68h Size: DESCRIPTION 74 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN9218i ...
Page 75
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9218i will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
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... TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9218i Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero. ...
Page 77
... Configurable FIFO Memory Allocation," on page 78 15-3 Reserved 2 32/16-bit Mode. When set, the LAN9218i is set for 32-bit operation. When clear configured for 16-bit operation. This field is the value of the D32/nD16 strap. 1 Soft Reset Time-out (SRST_TO software reset is attempted when the ...
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... DATASHEET Datasheet RX STATUS FIFO SIZE (BYTES) 13440 896 12480 832 11520 768 10560 704 9600 640 8640 576 7680 512 6720 448 5760 384 4800 320 3840 256 2880 192 1920 128 SMSC LAN9218i ...
Page 79
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9218i moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 80
... RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9218i Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO. 15-0 RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in bytes, used in the RX data FIFO ...
Page 81
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9218i Note: The LAN9218i must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS 31:14 ...
Page 82
... Device Ready (READY). When set, this bit indicates that LAN9218i is ready to be accessed. This register can be read when LAN9218i is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9218i has stabilized and is fully alive ...
Page 83
... GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as output. When cleared the GPIO is enabled as an input. GPIO0 – bit 8 GPIO1 – bit 9 GPIO2 – bit 10 7:5 Reserved SMSC LAN9218i 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 83 DATASHEET 32 bits ...
Page 84
... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION EEDIO FUNCTION EEDIO GPO3 Reserved GPO3 Reserved TX_EN TX_EN TX_CLK 8Ch Size: DESCRIPTION 84 DATASHEET Datasheet TYPE DEFAULT R/W 00 R/W 000 EECLK FUNCTION EECLK GPO4 RX_DV GPO4 RX_DV RX_CLK 32 bits TYPE DEFAULT R/W FFFFh SMSC LAN9218i ...
Page 85
... This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs inside the LAN9218i. The LAN9218i always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 86
... An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 9Ch Size: DESCRIPTION A0h Size: DESCRIPTION 86 DATASHEET Datasheet 32 bits TYPE DEFAULT bits TYPE DEFAULT RC 00000000h SMSC LAN9218i ...
Page 87
... MAC_CSR_DATA – MAC CSR Synchronizer Data Register Offset: This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s BITS 31-0 MAC CSR Data. Value read from or written to the MAC CSR’s. SMSC LAN9218i A4h Size: DESCRIPTION A8h Size: DESCRIPTION ...
Page 88
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9218i will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31:24 ...
Page 89
... Datasheet BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9218i will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9218i is operating in full-duplex mode. ...
Page 90
... After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support B0h Size: DESCRIPTION 90 DATASHEET Datasheet 32 bits TYPE DEFAULT SC 0 SMSC LAN9218i ...
Page 91
... MAC address from the EEPROM value of 0xA5 is not found in the first address of the EEPROM, the EEPROM is assumed to be un- programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. SMSC LAN9218i DESCRIPTION [28] OPERATION 0 READ ...
Page 92
... EEPROM Data. Value read from or written to the EEPROM. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 92 DATASHEET Datasheet TYPE DEFAULT R/ R/W 00h 32 bits TYPE DEFAULT RO - R/W 00h SMSC LAN9218i ...
Page 93
... FLOW 9 VLAN1 A VLAN2 B WUFF C WUCSR SMSC LAN9218i Map", shown below, lists the MAC registers that are Table 5.6 MAC CSR Register Map REGISTER NAME MAC Control Register MAC Address High MAC Address Low Multicast Hash Table High Multicast Hash Table Low MII Access ...
Page 94
... Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 1 Attribute: 00040000h Size: DESCRIPTION 94 DATASHEET Datasheet R/W 32 bits SMSC LAN9218i ...
Page 95
... Datasheet BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9218i will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 96
... Reserved 15-0 Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9218i device. The content of this field is undefined until loaded from the EEPROM at power- on. The host can update the contents of this field after the initialization process has completed. Revision 2.3 (08-06-08) ...
Page 97
... BITS 31-0 Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9218i device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. Table 5.7 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet physical address ...
Page 98
... Hash Table High Register" BITS 31-0 Lower 32 bits of the 64-bit Hash Table Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: 00000000h Size: for further details. DESCRIPTION 98 DATASHEET Datasheet R/W 32 bits R/W 32 bits Table 5.4.4, SMSC LAN9218i ...
Page 99
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9218i to read or write any of the MII PHY registers. ...
Page 100
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9218i will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 101
... VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. SMSC LAN9218i 9 Attribute: 00000000h Size: ...
Page 102
... Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support B Attribute: 00000000h Size: DESCRIPTION C Attribute: 00000000h Size: DESCRIPTION 102 DATASHEET Datasheet WO 32 bits R/W 32 bits SMSC LAN9218i ...
Page 103
... MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9218i PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 104
... The default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 0 Size: DESCRIPTION 104 DATASHEET Datasheet 16-bits TYPE DEFAULT RW/ See Note 5.1 RW See Note 5 RW/ SMSC LAN9218i ...
Page 105
... Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. 5.5.3 PHY Identifier 1 Index (In Decimal): BITS 15-0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. SMSC LAN9218i 1 Size: DESCRIPTION 2 Size: DESCRIPTION 105 DATASHEET 16-bits TYPE ...
Page 106
... Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 3 Size: DESCRIPTION 4 Size: DESCRIPTION 5.2) 106 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0xC0C3h RO RO 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W See Note 5.3 R/W 1 R/W See Note 5.3 R/W See Note 5.3 R/W 00001 SMSC LAN9218i ...
Page 107
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex 10Mbps with full duplex ability 5 10Base- 10Mbps able 10Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN9218i 5 Size: DESCRIPTION 107 DATASHEET 16-bits TYPE DEFAULT ...
Page 108
... The default value of this bit will vary dependant on the current link state of the line. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 6 Size: DESCRIPTION 17 Size: DESCRIPTION 108 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT See Note 5 SMSC LAN9218i ...
Page 109
... Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9218i in this mode. 111 All capable. Auto-negotiation enabled. Note 5.5 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto- negotiated speed and duplex. ...
Page 110
... Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 27 Size: DESCRIPTION 110 DATASHEET Datasheet 16-bits MODE DEFAULT RW, 0 NASR XXXXb SMSC LAN9218i ...
Page 111
... The default value of this bit will vary dependant on the current link state of the line. 5.5.12 Interrupt Mask Index (In Decimal): BITS 15-8 Reserved. Write as 0; ignore on read. 7-0 Mask Bits interrupt source is enabled 0 = interrupt source is masked SMSC LAN9218i 29 Size: DESCRIPTION 30 Size: DESCRIPTION 111 DATASHEET 16-bits ...
Page 112
... Reserved. Write as 0; ignore on Read Note 5.7 See Table 2.2, “Default Ethernet Settings,” on page Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 31 Size: DESCRIPTION 112 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 000b 0000010b RO See Note 5.7 RO 00b 15, for default settings. SMSC LAN9218i ...
Page 113
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9218i before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 114
... FOLLOWING ANY WRITE CYCLE (IN NS) 0 135 135 315 45 45 135 45 180 114 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING T OF 45NS) CYCLE SMSC LAN9218i ...
Page 115
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9218i, and the subsequent indication of the expected change in the control register values. ...
Page 116
... They may be asserted and deasserted in any order. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Figure 6.1 PIO Read Cycle Timing Table 6.3 PIO Read Timing 116 DATASHEET Datasheet MIN TYP MAX UNITS SMSC LAN9218i ...
Page 117
... Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN9218i Table 6.4 PIO Burst Read Timing MIN 117 ...
Page 118
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9218i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9218i ...
Page 119
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9218i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9218i ...
Page 120
... PIO Writes PIO writes are used for all LAN9218i write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are identical with the exception that D[31:16] are ignored during a 16-bit write ...
Page 121
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9218i will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9218i ...
Page 122
... Configuration input hold after nRESET rising T6.4 Output Drive after nRESET rising Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support T6.1 T6.2 T6.3 T6.4 Table 6.9 Reset Timing MIN TYP MAX 200 200 10 16 122 DATASHEET Datasheet UNITS NOTES SMSC LAN9218i ...
Page 123
... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9218i: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK ...
Page 124
... Operating Conditions** Supply Voltage (VDD_A, VDD_REF, VREG, VDD_IO +3.3V +/- 10% Ambient Operating Temperature in Still Air (T **Proper operation of the LAN9218i is guaranteed only within the ranges specified in this section. Revision 2.3 (08-06-08) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support (Note 7.1 .0V to +3.3V+10% (Note 7 ...
Page 125
... High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 7.3 Power Consumption (Device Only) This section provides typical power consumption values for the LAN9218i in various modes of operation. All of these values are preliminary. These measurements were taken under the following conditions: Temperature: ................................................................................................................................... +25°C Device VDD: ...
Page 126
... LAN9218i, including the power dissipated by the magnetics and other passive components. All of these values are preliminary. Please refer to the SMSC application note AN14.10 - “Migrating from LAN9118 to the LAN9218I”, that can be found on SMSC’s web site www.smsc.com, which contains additional details on magnetics and other components used ...
Page 127
... Worst Case Current Consumption Table 7.3 below lists the worst case current consumption for each of the supplies of the LAN9218i. These figures are provided to assist system designers properly design the power supply; they cannot be used to determine typical power consumption of the device. All of these values are preliminary. ...
Page 128
... DC Electrical Specifications This section details the DC electrical specifications of the LAN9218i I/O buffers. The electrical specifications in this section are valid over the voltage range and the temperature range specified in Section 7.2, "Operating PARAMETER SYMBOL I Type Input Buffer Low Input Level V ILI High Input Level ...
Page 129
... Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. SMSC LAN9218i input leakage for the entire device. This value should be divided by IN MAX to calculate per-pin leakage. For example pins IN ...
Page 130
... Clock Circuit The LAN9218i can accept either a 25MHz crystal (preferred MHz single-ended clock oscillator (±50 PPM) input. The LAN9218i shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3 ...
Page 131
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN9218i MAX REMARKS 1.60 Overall Package Height 0 ...
Page 132
... Input leakage current values added Added temperature range information Pin assignment information re-organized into separate table. Note added to EECLK pin description to indicate proper usage. 132 DATASHEET Datasheet CORRECTION WUCSR—Wake- Register, a broadcast wake- Register.” SMSC LAN9218i ...