74vcxh16240 Fairchild Semiconductor, 74vcxh16240 Datasheet
74vcxh16240
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74vcxh16240 Summary of contents
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... The VCXH16240 data inputs include active bushold cir- cuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic level. The 74VCXH16240 is designed for low voltage (1.65V to 3.6V) V applications with output capability up to 3.6V. CC ...
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... Connection Diagram Functional Description The 74VCXH16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are con- Logic Diagram www ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( – Output Voltage ( Outputs 3-STATED Outputs Active (Note 2) 0. Input ...
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DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current Control Pins I Data Pins I ...
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AC Electrical Characteristics Symbol Parameter Prop Delay PHL PLH Output Enable Time PZL PZH Output Disable Time PLZ PHZ t Output to Output Skew OSHL t (Note 14) OSLH Note 13: ...
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AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...