74VCXH16373MTD Fairchild Semiconductor, 74VCXH16373MTD Datasheet

74VCXH16373MTD

Manufacturer Part Number

74VCXH16373MTD

Description

IC LATCH TRANSP 16BIT LV 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXHr

Datasheet

1.74VCXH16373MTD.pdf (11 pages)

Specifications of 74VCXH16373MTD

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

1.2 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1.5ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74VCXH16373G

(Note 1)(Note 2)

74VCXH16373MTD

(Note 2)

74VCXH16373

Low Voltage 16-Bit Transparent Latch with Bushold

General Description

The VCXH16373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The VCXH16373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The 74VCXH16373 is designed for low voltage (1.2V to

3.6V) V

The 74VCXH16373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 1: Ordering Code “G” indicates Tray.

Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with output compatibility up to 3.6V.

Package Number

(Preliminary)

BGA54A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500229

Features

1.2V to 3.6V V

3.6V tolerant control inputs and outputs

Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

3.0 ns max for 3.0V to 3.6V V

Human body model

Machine model

24 mA @ 3.0V V

Package Description

to O

)

supply operation

)

200V

2000V

January 2000

Revised June 2005

www.fairchildsemi.com

Related parts for 74VCXH16373MTD

74VCXH16373MTD Summary of contents

Page 1

... BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) (Preliminary) 74VCXH16373MTD 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide MTD48 (Note 2) Note 1: Ordering Code “G” indicates Tray. Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Bushold Inputs –O Outputs ...

Page 3

Functional Description The 74VCXH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 4) 0. Input Diode Current ( ...

Page 5

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current Control Pins I Data Pins I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output ...

Page 6

AC Electrical Characteristics Symbol Parameter t , Propagation Delay C PHL PLH Propagation Delay C PHL PLH Output Enable Time C PZL t ...

Page 7

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL V Quiet Output Dynamic Valley V OHV OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT ...

Page 8

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low ...

Page 9

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A (Preliminary) 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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