lmh0040sqx National Semiconductor Corporation, lmh0040sqx Datasheet - Page 6

• Manufacturer Part Number: lmh0040sqx
• Description: Hd, Sd, Dvb-asi Sdi Serializer With Lvds Interface [preliminary]
• Manufacturer: National Semiconductor Corporation

www.national.com
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Note 1: “Absolute Maximum Ratings” are limits beyond which the safety of the device cannot be guaranteed. It is not implied that the device will operate up to
these limits.
Note 2: Typical Parameters measured at V
Note 3: Recommended value—Parameter is not tested.
Note 4: Recommended maximum capacitance load per bus segment is 400 pF.
Note 5: Maximum termination voltage should be identical to the device supply voltage.
Note 6: Measured in accordance with SMPTE RP184.
Device Operation
The LMH0040 serializer is used in digital video signal origi-
nation equipment. It is intended to be operated in conjunction
with an FPGA host which preprocesses data for it, and then
provides this data over the five bit wide datapath. Provided
the host has properly formatted the data for the LMH0040, the
output of the device will be compliant with DVB-ASI, SMPTE
259M-C, SMPTE 292M or SMPTE 424M depending upon the
output mode selected.
Power Supplies
The LMH0040 has several power supply pins, at 2.5V as well
as 3.3V. It is important that these pins all be connected, and
properly bypassed. Bypassing should consist of parallel 4.7
μF and 0.1 μF capacitors as a minimum, with a 0.1 μF ca-
pacitor on each power pin. The device has a large contact in
the center of the bottom of the package. This contact must be
connected to the system GND as it is the major ground con-
nection for the device.
Power Up
After the transmitter/receiver is powered up, it goes through
a power-on reset procedure, and then enters the link acqui-
sition mode. The transmitter will first acquire the input data
and clock, and once this has happened, the transmitter will
begin sending serialized data. The data is serialized with the
TXIN0 bit being transmitted first, and TXIN4 being the last bit
transmitted.
LVDS Inputs
The LMH0040 has standard 3.3V LVDS inputs and is com-
pliant with ANSI/TIA/EIA-644. These inputs have an internal
100Ω resistor across the inputs which allows for the closing
of a current loop interface from the LVDS driver in the host. It
Symbol
Peak to Peak Alignment Jitter
Output Return Loss
Output Overshoot
Parameter
DD
=3.3V, T
FIGURE 4. LVDS Interface Propagation Delay
A
=25°C. They are for reference purposes and are not production tested.
≥
≤
Measured 5 MHz to 1483 MHz
1,483 Mbps (Note 6)
1,483 Mbps (Note 6)
Condition
6
is recommended that the PCB trace between the FPGA and
the transmitter be less than 25 cm. Longer PCB traces may
introduce signal degradation as well as channel skew which
could cause serialization errors. This connection between the
host and the LMH0040 should be over a controlled
impedance transmission line with an impedance which
matches the termination resistor—usually 100Ω.
DVB_ASI Mode
The LMH0040 has a special mode for DVB-ASI. In this mode,
the input signal on TX4+/TX4- is treated as a data valid bit, if
high, then the four bit nibbles from TX0–TX3 are taken to form
an 8 bit word, which is then converted to a 10 bit code via an
internal 8b10b encoder and this 10 bit word is serialized and
driven on the output. The nibble taken in on the rising edge of
the clock is the most significant nibble and the nibble taken in
on the falling edge is the least significant nibble. If TX4+/TX4-
is low, then the input on TX0–TX3 are ignored and the 10b
idle character is inserted in the output stream.
SDI Output Interfacing
The serial outputs provide low-skew complimentary or differ-
ential signals. The output buffer is a current mode design, with
a high impedance output. To drive a 75Ω transmission line
connect a 75Ω resistor from each of the output pins to 2.5V.
This resistor has two functions—it converts the current output
to a voltage, which is used to drive the cable, and it acts as
the back termination resistor for the transmission line. The
resistor should be placed as close to the output pin as is prac-
ticable. The output driver automatically adjusts its slew rate
depending on the input datarate so that it will be in compliance
with SMPTE 259M, SMPTE292M or SMPTE 424M as appro-
priate. In addition to output amplitude and rise/fall time spec-
ifications, the SMPTE specs require that SDI outputs meet an
Output Return Loss (ORL) specification. There are parasitic
capacitances that will be present both at the output pin of the
Min
15
(Note 2)
Typ
5.3
20
Max
0.09
60
8
30017005
Units
dB
ps
UI
%