u6264asa07 ETC-unknow, u6264asa07 Datasheet

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u6264asa07

Manufacturer Part Number
u6264asa07
Description
Automotive Sram
Manufacturer
ETC-unknow
Datasheet
Features
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December 12, 1997
Pin Configuration
8192 x 8 bit static CMOS RAM
70 ns Access Time
Common data inputs and outputs
Three-state outputs
Typ. operating supply current:
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: SOP28 (300 mil)
DQ1
DQ2
DQ0
VSS
A12
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
-40 to 125 C
30 mA
11
1
2
3
4
5
6
7
8
9
10
12
13
14
Top View
SOP28 (330 mil)
SOP
27
22
15
28
26
25
24
23
21
20
19
18
17
16
DQ3
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
Description
The U6264ASA07 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Write
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
- Standby
- Data Retention
1
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Automotive 8K x 8 SRAM
Signal Description
Address Inputs
Data In/Outputs
Chip Enable 1
Chip Enable 2
Output Enable
Read/Write Enable
Power Supply Voltage
Ground
not connected
change, the data outputs go High-Z
until the new read information is
available. The full CMOS data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the ope-
rating current (at I
to the value of the operating current
in the Standby mode. The Read
cycle is finished by the falling edge
of E2 or W, or by the rising edge of
E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
If the circuit is inactivated by E2 = L,
the standby current (TTL) drops to
150 A typ.
U6264ASA07
O
= 0 mA) drops

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u6264asa07 Summary of contents

Page 1

... DQ4 VSS 14 15 DQ3 Top View December 12, 1997 Automotive SRAM Description The U6264ASA07 is a static RAM manufactured using a CMOS pro- cess technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge L), or the falling edge ...

Page 2

... U6264ASA07 Block Diagram A11 A12 A10 E2 E1 Truth Table Operating Mode E1 * Standby/not selected H Internal Read L Read L Write Characteristics All voltages are referenced (ground). SS All characteristics are valid in the power supply voltage range and in the operating temperature range specified. ...

Page 3

... CC(DR 5.5 V OHZ 5 5.5 V OLZ U6264ASA07 Min. Max. Unit 4.5 5 -0.3 0.8 V 2 Min. Max. Unit ...

Page 4

... U6264ASA07 Switching Characteristics Time to Output in Low-Z Cycle Time Write Cycle Time Read Cycle Time Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid Pulse Widths Write Pulse Width Chip Enable to End of Write Setup Times Address Setup Time ...

Page 5

... DQ6 A10 DQ7 A11 A12 the capacitance is 5 pF. dis(G) Conditions Symbol MHz U6264A U6264ASA07 5 V 960 510 Min. Max. Unit Internal Code Access Time ...

Page 6

... U6264ASA07 Read Cycle 1 (during Read cycle Output Read Cycle 2 (during Read cycle Output Write Cycle 1 (W-controlled AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA E1 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 7

... AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A AAAA AAAA AAAA AAAA H-level AAAA AAAA A A AAAA AAAA 7 U6264ASA07 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...

Page 8

... Memory Products 1998 Automotive SRAM U6264ASA07 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur ...

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