pi2eqx3232a Pericom Semiconductor Corporation, pi2eqx3232a Datasheet - Page 2

• Manufacturer Part Number: pi2eqx3232a
• Description: 4-channel Sas/satax Redriver/equalizer With Flow-through Pinout
• Manufacturer: Pericom Semiconductor Corporation

Pin Description
25, Center Pad
41, 40, 39, 38
Pin #
36
35
33
32
14
15
30
29
27
26
10
11
13
24
22
23
47
46
16
17
1
2
4
5
7
8
07-0189
SEL_EQ_D
SEL_EQ_A
SEL_EQ_B
SEL_EQ_C
Pin Name
[A,B,C,D]
EN_CLK
CKIN+
CKIN-
OUT+
OUT-
GND
IREF
AO+
BO+
CO+
DO+
EN_
AO-
BO-
CO-
DO-
AI+
BI+
CI+
DI+
AI-
BI-
CI-
DI-
PWR
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Positive CML Input Channel A with internal 50Ω pull down
Negative CML Input Channel A with internal 50Ω pull down
Positive CML Output Channel A internal 50Ω pull up to VDD during normal opera-
tion and 2kΩ when EN_A=0. Drives to output common mode voltage when input is
<V
Negative CML Output Channel A with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_A=0. Drives to output common mode voltage when
input is <V
Positive CML Input Channel B with internal 50Ω pull down
Negative CML Input Channel B with internal 50Ω pull down
Positive CML Output Channel B with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_B=0. Drives to output common mode voltage when
input is <V
Negative CMLOutput Channel B with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_B=0. Drives to output common mode voltage when
input is <V
Positive CML Input Channel C with internal 50Ω pull down
Negative CML Input Channel C with internal 50Ω pull down
Differential Input Reference Clock The clock buffer is provided for general use, and
is not needed for data channel operation.
Positive CMLOutput Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_C=0. Drives to output common mode voltage when
input is <V
Negative CMLOutput Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_C=0. Drives to output common mode voltage when
input is <V
Positive CML Input Channel D with internal 50Ω pull down
Negative CML Input Channel D with internal 50Ω pull down
Positive CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2kΩ pull up when EN_C=0. Drives to output common mode voltage when input
is <V
Negative CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2kΩ pull up when EN_C=0. Drives to output common mode voltage when input
is <V
Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output.
When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- out-
puts will be pulled up to V
Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTx-
outputs. When LOW, it disables these outputs, with 50Ω to ground termination.
Supply Ground
External 475Ω resistor connection to set the differential output current
Differential Reference Clock Output
Selection pins for equalizer (see Equalizer Selection Table)
w/ 50kΩ internal pull up
TH–
TH–
TH–
.
..
..
TH–
TH–
TH–
TH–
TH–
.
.
.
.
.
2
DD
by internal 2kΩ resistor.
Description
3.2Gbps, 2-Port, SATA/SAS,
Serial Re-Driver
PI2EQX3232A
PS8904A
09/25/07