pi2eqx5804nje Pericom Semiconductor Corporation, pi2eqx5804nje Datasheet - Page 5

• Manufacturer Part Number: pi2eqx5804nje
• Description: 5.0gbps 4-lane Pcie Gen2 Redriver
• Manufacturer: Pericom Semiconductor Corporation

Equalizer Confi guration
The PI2EQX5804 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) re-
sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-
frequency signal components. Because either too little, or too much, signal compensation may be non-optimal
eight levels are provided to adjust for any application.
Equalizer confi guration is performed in two ways determined by the state of the MODE pin. When the device
fi rst powers up, the SELx_[A:B] input pins are read into the appropriate control registers to set the equalization
characteristic. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
Each group of four channels, A and B, has separate equalization control, and all four channels within the group
are assigned the same confi guration state. The Equalizer Selection table below describes pin strapping options
and associated operation of the equalizer. Refer to the section on I2C programming for information on soft-
ware confi guration of the equalizer.
Equalizer Selection
Output Confi guration
The PI2EQX5804 provides fl exible output strength and emphasis controls to provide the optimum signal to
pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean with good
eye opening. Control of output confi guration is grouped for the A and B channels, so that each channel within
the group has the same setting.
Output confi guration is performed in two ways depending on the state of the MODE pin. When the device
fi rst powers up, the Sx_[A:B], and Dx_[A:B] input pins are read into the appropriate control registers to set the
power-on state. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
The Output Swing Control table shows available confi guration settings for output level control, as specifi ed
using the Sx_y pins and registers.
SEL2_[A:B]
0
0
0
0
1
1
1
1
07-0260
SEL1_[A:B]
0
0
1
1
0
0
1
1
SEL0_[A:B]
0
1
0
1
0
1
0
1
5
5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
Equalization & Emphasis
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
PS8926A
PI2EQX5804
11/19/07