pi2eqx5864d Pericom Semiconductor Corporation, pi2eqx5864d Datasheet - Page 8

• Manufacturer Part Number: pi2eqx5864d
• Description: 5.0gbps 4-lane Pcie? 2.0 Redrivertm With Equalization, Emphasis, & I2c Control
• Manufacturer: Pericom Semiconductor Corporation

Configuration Register Summary
I
The PI2EQX5864D I
mode. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from the lowest to the highest byte with
the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are programmable to support multiple
chips environment. The data is loaded until a Stop sequence is issued.
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the
most significant bit (MSB) first (see the I
force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of configuration bytes. An
offset byte presented by a host to the PI2EQX5864D is not used.
Addressing
Up to eight PI2EQX5864D devices can be connected to a single I
indicating either a read or write operation. The address for a specific device is determined by the A0, A1 and A4 input pins.
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0
1
2
3
4
5
6
7
8
9
10
11
2
Byte Mnemonic
A6
1
Address Assignment
C Operation
SIG
RX50
LBEC
INDIS
OUTDIS
RESET
PWR
RXDE
AEOC
BEOC
RSVD
RSVD
A5
1
2
C controller operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing
Function
Signal Detect, indicates valid input signal level
Receiver Detect Output, indicates whether a receiver load was detected
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre-
emphasis or de-emphasis)
Channel Input Disable, controls whether a channels input buffer is enabled or disabled
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
Channel Reset
Power Down Control, enables power down for each channel individually
Receiver Detect Enable, controls the receiver detect operation
A-Channels Equalizer and Output Control
B-Channels Equalizer and Output Control
Reserved
Reserved
A4
Program
2
C Data Transfer diagram). The PI2EQX5864D will never hold the clock line SCL LOW to
A3
0
10-0172
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
2
8
C bus. The PI2EQX5864D supports 7-bit addressing, with the LSB
A2
0
A1
Programmable
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A0
PI2EQX5864D
PS 0.1
R/W
1=R, 0=W
06/04/10