ncn6001 ON Semiconductor, ncn6001 Datasheet - Page 19

• Manufacturer Part Number: ncn6001
• Description: Compact Smart Card Interface Ic
• Manufacturer: ON Semiconductor

SPI PORT
microcontroller by means of a serial link using a
Synchronous Port Interface protocol, the CLK_SPI being
Low or High during the idle state. The NCN6001 is not
intended to operate as a Master controller, but execute
commands coming from the MPU.
microcontroller’s responsibility. The MISO signal is
generated by the NCN6001, using the CLK_SPI and CS
on the SPI port. The two data lines becomes active when
CS = Low, the internal shift register is cleared and the
communication is synchronized by the negative going edge
of the CS signal. The data present on the MOSI line is
considered valid on the negative going edge of the CLK_SPI
clock and is transferred to the shift register on the next
positive edge of the same CLK_SPI clock.
The
The CLK_SPI, the CS and the MOSI signals are under the
When the CS line is High, no data can be written or read
RST_COUNTER
ADDRESS
DECODE
product
SPI_CLK
SPI_CLK
MOSI
MISO
MOSI
MISO
CS
CS
NCN6001 Sends Bit
from READ_REG
MPU Enables Clock
MPU Sends Bit
communicates
MPU Enables
Figure 12. Chip Address Decoding Protocol and MISO Sequence
MPU Asserts Chip Set
MPU Asserts Chip Select
MISO Line = High Impedance
Clock
to
Figure 11. Basic SPI Timings and Protocol
B7
MSB
the
ADDRESS
B6
CHIP
NCN6001 Reads Bit
MPU Reads Bit
external
http://onsemi.com
B5
NCN6001
19
B4
The Chip Address is decoded on the third clock pulse.
COMMAND AND CONTROL
lines to synchronize the bits carried out by the data byte. The
basic timings are given in Figure 11 and Figure 12. The
system runs with two internal registers associated with the
MOSI and MISO data:
WRT_REG is a write only register dedicated to the MOSI
data.
READ_REG is a read only register dedicated to the MISO
data.
internal logic identifies the chip address on the fly (reading
and decoding the three first bits) and validates the right data
present on the line. Consequently, the data format is MSB
first to read the first three signal as bits B5, B6 and B7. The
chip address is decoded from this logic value and validates
the chip according to the C4 and C8 conditions (Figure 12).
The MISO signal is activated and data transferred
To accommodate the simultaneous MISO transmit, an
B3
B2
B1
B0
LSB
tclr