tc74hc107af TOSHIBA Semiconductor CORPORATION, tc74hc107af Datasheet

tc74hc107af

Manufacturer Part Number

tc74hc107af

Description

Dual J-k Flip Flop With Clear

Manufacturer

TOSHIBA Semiconductor CORPORATION

Datasheet

1.TC74HC107AF.pdf (10 pages)

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Dual J-K Flip Flop with Clear

FLOP fabricated with silicon gate C

LSTTL while maintaining the CMOS low power dissipation.

inputs, the outputs change state on the negative going transition

of the clock pulse.

logic level on the input.

discharge or transient excess voltage.

Features

•

Pin Assignment

IEC Logic Symbol

The TC74HC107A is a high speed CMOS DUAL J-K FLIP

It achieves the high speed operation similar to equivalent

In accordance with the logic levels applied to the J and K

All inputs are equipped with protection circuits against static

CLR is independent of the clock and is accomplished by a low

High speed: f

Low power dissipation: I

High noise immunity: V

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I

Balanced propagation delays: t

Wide operating voltage range: V

Pin and function compatible with 74LS107

TC74HC107AP,TC74HC107AF,TC74HC107AFN

max

= 75 MHz (typ.) at V

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

NIH

= 2 µ A (max) at Ta = 25°C

= V

pLH

NIL

MOS technology.

∼ − t

(opr) = 2~6 V

= 28% V

| = I

pHL

= 5 V

= 4 mA (min)

(min)

Note: xxxFN (JEDEC SOP) is not available in

Weight

DIP14-P-300-2.54

SOP14-P-300-1.27A

SOP14-P-300-1.27

SOL14-P-150-1.27

TC74HC107AP

TC74HC107AF

TC74HC107AFN

Japan.

TC74HC107AP/AF/AFN

: 0.96 g (typ.)

: 0.18 g (typ.)

: 0.12 g (typ.)

2006-06-01

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tc74hc107af Summary of contents

Page 1

... IEC Logic Symbol Note: xxxFN (JEDEC SOP) is not available in TC74HC107AP TC74HC107AF = 28% V (min (min ∼ − t pHL (opr) = 2~6 V TC74HC107AFN Weight DIP14-P-300-2.54 SOP14-P-300-1.27A SOP14-P-300-1.27 SOL14-P-150-1.27 1 TC74HC107AP/AF/AFN Japan. : 0.96 g (typ.) : 0.18 g (typ.) : 0.18 g (typ.) : 0.12 g (typ.) 2006-06-01 ...

Page 2

Truth Table Inputs Outputs CLR Don’t care ...

Page 3

Recommended Operating Conditions (Note) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Note: The recommended operating conditions are required to ensure the normal operation of the device. Unused inputs must be tied to either ...

Page 4

Timing Requirements (input: t Characteristics Symbol Minimum pulse width Minimum pulse width t ( CLR ) Minimum set-up time Minimum hold time Minimum removal time ( CLR ) Clock frequency = 15 pF ...

Page 5

AC Characteristics (C L Characteristics Symbol t TLH Output transition time t THL Propagation delay t pLH time t pHL ( CK - Propagation delay t pLH time t pHL ( CLR -Q, ...

Page 6

Package Dimensions Weight: 0.96 g (typ.) TC74HC107AP/AF/AFN 6 2006-06-01 ...

Page 7

Package Dimensions Weight: 0.18 g (typ.) TC74HC107AP/AF/AFN 7 2006-06-01 ...

Page 8

Package Dimensions Weight: 0.18 g (typ.) TC74HC107AP/AF/AFN 8 2006-06-01 ...

Page 9

Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.12 g (typ.) TC74HC107AP/AF/AFN 9 2006-06-01 ...

Page 10

Note: Lead (Pb)-Free Packages DIP14-P-300-2.54 SOP14-P-300-1.27A SOL14-P-150-1.27 RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in ...

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