lm48823tlx National Semiconductor Corporation, lm48823tlx Datasheet - Page 10

• Manufacturer Part Number: lm48823tlx
• Description: Mono, Bridge-tied Load, Ceramic Speaker Driver With I2c Volume Control And Reset
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
I
The LM48823 is controlled through an I
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open drain). The LM48823 and the master can
communicate at clock rates up to 400kHz. Figure 2 shows the
I
stable during the HIGH period of SCL. The LM48823 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition (Figure
3). Each data word, device address and data, transmitted
over the bus is 8 bits long and is always followed by an ac-
knowledge pulse (Figure 4). The LM48823 device address is
1110110.
I
The I
the transition of SDA from HIGH to LOW while SCL is HIGH,
is generated, alerting all devices on the bus that a device ad-
dress is being written to the bus.
2
2
2
C COMPATIBLE INTERFACE
C interface timing diagram. Data on the SDA line must be
C BUS FORMAT
2
C bus format is shown in Figure 4. The START signal,
2
C compatible serial
FIGURE 3. Start and Stop Diagram
FIGURE 2. I
2
C Timing Diagram
10
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the
master is writing to the slave device, R/W = 1 indicates the
master wants to read data from the slave device. Set R/W =
0; the LM48823 is a WRITE-ONLY device and will not re-
spond to the R/W = 1. The data is latched in on the rising edge
of the clock. Each address bit must be stable while SCL is
HIGH. After the last address bit is transmitted, the master de-
vice releases SDA, during which time, an acknowledge clock
pulse is generated by the slave device. If the LM48823 re-
ceives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. After the 8-bit register data word is sent, the
LM48823 sends another ACK bit. Following the acknowl-
edgement of the register data word, the master issues a
STOP bit, allowing SDA to go high while SCL is high.
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