lm49100gr National Semiconductor Corporation, lm49100gr Datasheet - Page 16

• Manufacturer Part Number: lm49100gr
• Description: Mono Class Ab Audio Subsystem With A True-ground Headphone Amplifier
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
MINIMIZING CLICK AND POP
To minimize the audible click and pop heard through a head-
phone, maximize the input signal through the corresponding
volume (gain) control registers and adjust the output amplifier
gain accordingly to achieve the user’s desired signal gain. For
example, setting the output of the headphone amplifier to
-24dB and setting the input volume control gain to 24dB will
reduce the output offset from 7mV (typical) to 2.2mV (typical).
This will reduce the audible click and pop noise significantly
while maintaining a 0dB signal gain.
SIGNAL GROUND NOISE
The LM49100 has proprietary suppression circuitry, which
provides an additional -50dB (typical) attenuation of the head-
phone ground noise and its incursion into the headphone. For
optimum utilization of this feature the headphone jack ground
should connect to the AGND (E3) bump.
I
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADDR: This is the address select input pin.
I
The LM49100 uses a serial bus which conforms to the I
protocol to control the chip's functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The LM49100's
I
(400kHz) I
controlling microcontroller and the slave is the LM49100.
The I
ADDR pin. The LM49100's two possible I
2
2
2
C PIN DESCRIPTION
C COMPATIBLE INTERFACE
C compatible interface supports standard (100kHz) and fast
2
C address for the LM49100 is determined using the
2
C modes. In this discussion, the master is the
300015m9
2
C chip addresses
FIGURE 2. I
2
C
2
16
C Bus Format
are of the form 111110X
is logic LOW; and X
I
the LM49100's chip address can be changed to avoid any
possible address conflicts.
The bus format for the I
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is HIGH. The start signal will alert all
devices attached to the I
against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is HIGH.
After the last bit of the address bit is sent, the master releases
the data line HIGH (through a pull-up resistor). Then the mas-
ter sends an acknowledge clock pulse. If the LM49100 has
received the address correctly, then it holds the data line LOW
during the clock pulse. If the data line is not held LOW during
the acknowledge clock pulse, then the master should abort
the rest of the data transfer to the LM49100.
The 8 bits of data are sent next, most significant bit first. Each
data bit should be valid while the clock level is stable HIGH.
After the data byte is sent, the master must check for another
acknowledge to see if the LM49100 received the data.
If the master has more data bytes to send to the LM49100,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes HIGH while the clock signal is HIGH. The data
line should be held HIGH when not in use.
I
The LM49100's I
I
level set by the V
that of the main power supply pin V
logic levels for the I
troller or microprocessor that is operating at a lower supply
voltage than the main battery of a portable system.
2
2
2
C interface is used to address a number of chips in a system,
C INTERFACE POWER SUPPLY PIN (V
C pin. The LM49100's I
2
DD
C interface is powered up through theV
2
I
1
C interface are dictated by a microcon-
2
C pin which can be set independent to
= 1, if ADDR pin is logic HIGH. If the
2
2
1
C interface is shown in Figure 2. The
C bus to check the incoming address
0 (binary), where X
2
C interface operates at a voltage
DD
. This is ideal whenever
DD
1
= 0, if ADDR pin
I
2
C)
300015d5
DD