clc449 National Semiconductor Corporation, clc449 Datasheet - Page 9

• Manufacturer Part Number: clc449
• Description: 1.1ghz Ultra-wideband Monolithic Op Amp
• Manufacturer: National Semiconductor Corporation

Application Division
The normalized gain plots in the Typical Performance
Characteristics section show different feedback resistors R
for different gains. These values of R
obtaining the highest bandwidth with minimal peaking. The
resistor R
input.
For |A
R
minimum recommended R
Select R
At large gains, R
stage. This situation is resolved by driving R
impedance buffer like the CLC111, or increasing R
see the Bandwidth (Small Signal) sub-section for the
tradeoffs).
Accurate DC gain is usually limited by the tolerance of the
external resistors R
Bandwidth (Small Signal)
The CLC449 current-feedback amplifier bandwidth is a
function of the feedback resistor (R
gain (A
1/R
Other AC specifications will also be degraded. Decreasing
R
for very small values of R
With an inverting amplifier design, peaking is sometimes
observed. This is often the result of layout parasitics caused
by inadequate ground planes or long traces. If this is
observed, placing a 50 to 200
non-inverting pin and ground will usually reduce the peaking.
Bandwidth (Minimum Slew Rate)
Slew rate influences the bandwidth for large signal
sinusoids. To determine an approximate value of slew rate,
necessary to support large sinusoids use the following
equation:
V
of the sinusoid.
The slew rate of the CLC449 in inverting gains is always
higher than in non-inverting gains.
DC Design (Level Shifting)
Figure 3 shows a DC level shifting circuit for inverting gain
configurations. V
which is independent of the DC output produced by V
peak
f
f
from the recommended value increases peaking and
) 295 − |A
f
. As a rule, if R
is the peak output sinusoid voltage, f is the frequency
v
| 4, calculate the recommended R
v
). The bandwidth is approximately proportional to
g
t
to set the DC gain:
in Figure 2 provides DC bias for the non-inverting
V
| x R
g
ref
becomes small and will load the previous
f
produces a DC output level shift of
f
and R
SR)5 x f x V
doubles, the bandwidth is cut in half.
i
where R
f
g
is 100 .
.
f
oscillation will occur.
i
= 45 . For |A
peak
(Continued)
f
), not of the DC voltage
f
resistor between the
are recommended for
f
as follows:
g
with a low
V
|
f
>
and R
4, the
in
.
g
f
9
DC Design (Single Supply)
Figure 4 is a typical single-supply circuit. Resistors R
R
voltage. This circuit has a DC gain of 1. The coupling
capacitor C
stage. Both capacitors make a high pass response; the high
frequency gain is determined by R
The complete gain equation for the circuit in Figure 4 is
where s = j ,
DC Design (DC Offsets)
The DC offset model shown in Figure 5 is used to calculate
the output offset voltage. The equation for output offset
voltage is:
V
The current offset terms, I
other. The specifications are stated in terms of magnitude
only. Therefore, the terms V
positive or negative polarity. Matching the equivalent
resistance seen at both input pins does not reduce the
output offset voltage.
o
2
form a voltage divider that sets the non-inverting input DC
V
in
V
V
ref
V
in
V
V
os
in
o
C
1
FIGURE 3. Level Shifting Circuit
FIGURE 4. Single Supply Circuit
1
isolates the DC bias point from the previous
I
1
BN
R
R
R
1 s
= (R
1
2
eq1
V
s
R
cc
1
eq1
1
\R
1
2
R
) x C
C
CLC449
+
-
BN
g
1 s
OS
2
1
CLC449
, I
-
+
and I
1
, and
R
BN
V
R
eq2
1 s
f
, and I
2
cc
f
and R
BI
R
, do not track each
f
2
1
R
= R
BI
g
2
f
I
BI
.
may have either
R
g
R
DS012715-31
C
R
g
f
2
.
f
www.national.com
DS012715-32
V
o
V
1
o
and