z87001 ZiLOG Semiconductor, z87001 Datasheet - Page 30

• Manufacturer Part Number: z87001
• Description: Romless Spread Spectrum Cordless Phone Controller
• Manufacturer: ZiLOG Semiconductor

Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Sleep Mode
To save the phone’s battery life on the handset, the
Z87001 can be operated in sleep mode while the phone is
not in use. The sleep mode is entered by software com-
mand. The sleep mode first needs to be enabled by setting
the SLEEP_WAKE field. Then a GO_TO_SLEEP com-
mand puts the processor to sleep by temporarily stopping
its clock. The sleep period can be set to last between 4 ms
and 1.02 s by programming the SLEEP_PERIOD field. In
sleep mode, the RFEON pin is de-asserted.
The processor comes out of sleep mode in one of two
ways. Either the sleep counter counts down to zero, or one
of the enabled pins from port P0 is asserted prior to normal
expiration of the counter. Four port pins (P0[0..4]) can be
individually enabled to provide the wake-up function by
setting the appropriate bits in P0_WAKE_ENABLE. Typi-
cally, these port pins are connected to the telephone key-
pad.
When the processor core wakes up, the software needs to
know how much time it was actually asleep, in order to re-
store synchronization to the base station’s hopping se-
quence. For that purpose, the current value of the sleep
counter
SLEEP_REMAINING. A value of zero indicates normal ex-
piration of the sleep counter.
In order to guarantee a good operation of the wake-up
pins, the wake-up signals are hardware-denounced by the
Z87001. Furthermore, these signals are internally syn-
chronized to the bit clock. This ensures that the processor
has enough time (one bit time = 10.74 ms) to read a stable
value of the remaining sleep time and synchronize correct-
ly to the base station’s hopping sequence.
SLEEP_EAKE
GO_TO_SLEEP
SLEEP_PERIOD
SLEEP_REMAINING
P0_WAKEUP_ENABLE
ADPCM Processor Interface and Rate Buffers
The interface to the ADPCM Processor (Z87010) consists
of clock control, command/status interface and data inter-
face. The data interface gives the ADPCM Processor ac-
cess to the rate buffers.
30
Field
Table 5. Sleep Mode Control Fields
is
available
SSPSTATE
CONFIG2
CONFIG2
SSPSTATE
CONTROL
Register
to
the
Bank
processor
3
3
3
3
1
P R E L I M I N A R Y
EXT2
EXT2
EXT1
EXT1
EXT6
Ext
in
Clock Interface
The Z87001 generates the Z87010 clock at 16.384 or
8.192 MHz, as set in VP_CLOCK. In addition, the clock
can be stopped and restarted with the VP_STOP_CLOCK
field in order to reduce power consumption (Note: a soft-
ware handshaking between Z87001 and Z87010 is neces-
sary before stopping and after restarting the clock).
In addition to providing the Z87010 main clock, the Z87001
generates a CODCLK signal which will be used by the co-
dec and by the Z87010 to synchronize its data transfers
with the Z87001. On the base station, the CODCLK is sim-
ply obtained by dividing the 16.384 MHz input clock.
On the handset, the CODCLK is synchronized to the base
station’s CODCLK signal through the receive bit sync log-
ic. This ensures that production and consumption of voice
data is happening at identical rates on handset and base,
eliminating buffer overrun and underrun situations.
Command/Status Interface
The Z87001 sends commands to the Z87010 through the
VP_COMMAND write-only field. It reads the Z87010 sta-
tus in the VP_STATUS read-only field. Both fields are lo-
cated at the same address in the Z87001 register inter-
face. A communication protocol should be established in
software to ensure correct reception of all commands.
Dedicated hardware ensures data integrity when both
Z87001 and Z87010 simultaneously access the same reg-
ister.
VP_CLOCK
VP_STOP_CLCOCKS SSPSTATE
VP_COMMAND
VP_STATUS
Data Interface and Rate Buffers
The digitized voice data is communicated between the
Z87001 and Z87010 through the rate buffers and ADPCM
Processor data interface. The transmit and receive rate
buffers each contain 36 4-bit nibbles.
To write to the transmit rate buffer, the Z87001 core pro-
cessor must first set the nibble address in the
TX_BUF_ADDR register field, then write the nibble data
through TX_BUF_DATA. If the TX_AUTO_INCREMENT
bit is set, the address is automatically incriminated (modu-
lo 51 = the number of nibbles in rate buffer + 15 additional
data words accessible through TX_BUF_DATA; for more
information, see Register Description) after each data
write. This allows the DSP core to write successive nibbles
without resetting the address each time.
Table 6. ADPCM Processor Control Fields
Field
CONFIG1
VP_INOUT
VP_INOUT
Register
Bank
DS96WRL0800
3
3
2
2
EXT0
EXT2
EXT0
EXT0
Ext
Zilog