dm74ls162a National Semiconductor Corporation, dm74ls162a Datasheet - Page 3

• Manufacturer Part Number: dm74ls162a
• Description: Synchronous Presettable Bcd Decade Counters
• Manufacturer: National Semiconductor Corporation

Symbol
I
I
I
I
I
I
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
I
IH
IL
OS
CCH
CCL
Switching Characteristics
Functional Description
The ’LS160 and ’LS162 count modulo-10 in the BCD (8421)
sequence From state 9 (HLLH) they increment to state 0
(LLLL) The ’161 and ’163 count modulo-16 binary se-
quence From state 15 (HHHH) they increment to state 0
(LLLL) The clock inputs of all flip-flops are driven in parallel
through a clock buffer Thus all changes of the Q outputs
(except due to Master Reset of the ’LS160) occur as a re-
sult of and synchronous with the LOW-to-HIGH transition
of the CP input signal The circuits have four fundamental
modes of operation in order of precedence asynchronous
reset (’LS160) synchronous reset (’LS162) parallel load
count-up and hold Five control inputs Master Reset (MR
’LS160) Synchronous Reset (SR ’LS162) Parallel Enable
(PE) Count Enable Parallel (CEP) and Count Enable Trickle
(CET) determine the mode of operation as shown in the
Symbol
f
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PHL
Input Current
Input Voltage
High Level Input Current
Low Level Input Current
Short Circuit
Output Current
Supply Current with
Outputs HIGH
Supply Current with
Outputs LOW
Parameter
Maximum Clock Frequency
Propagation Delay
CP to TC
Propagation Delay
CP to Q
Propagation Delay
CET to TC
Propagation Delay
MR to Q
Max
n
Parameter
n
(’160)
V
V
V
PE CET Inputs
V
(Note 2)
V
CP
V
CP
CC
CC
CC
CC
CC
CC
V
e
e
CC
e
e
e
e
e
e
L Other Inputs
L
Max V
Max V
Max V
Max
Max PE
Max V
e a
5 0V T
I
I
I
IN
Conditions
e
e
e
e
e
7V
2 7V
0 4V Inputs
GND
GND
A
e a
3
e
Mode Select Table A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (P
flip-flops on the next rising edge of CP With PE and MR
(’LS160) or SR (’LS162) HIGH CEP and CET permit count-
ing when both are HIGH Conversely a LOW signal on ei-
ther CEP or CET inhibits counting
The ’LS160A and ’LS162A use D-type edge-triggered flip-
flops and changing the SR PE CEP and CET inputs when
the CP is in either state does not cause errors provided that
the recommended setup and hold times with respect to the
rising edge of CP are observed
25 C
4 5V
PE CET Inputs
PE CET Inputs
Min
25
54LS
DM74
54LS
DM74
Other
Other
C
R
L
L
e
e
15 pF
2 kX
b
b
Min
20
20
Max
n
25
21
24
27
14
23
28
) inputs to be loaded into the
(Note 1)
Typ
b
b
b
b
b
Max
0 1
0 2
20
40
31
31
100
100
0 4
1 6
0 8
Units
MHz
ns
ns
ns
ns
Units
mA
mA
mA
mA
mA
mA
mA