at25df641 ATMEL Corporation, at25df641 Datasheet
at25df641
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at25df641 Summary of contents
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... Very Thin DFN ( mm) 1. Description The AT25DF641 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...
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... To take code and data protection to the next level, the AT25DF641 incorporates a sector lock- down mechanism that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only. This addresses the need of certain secure applications that ...
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... WP pin. WP The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However recommended that the WP pin also be externally connected to V whenever possible. CC 3680B–DFLASH–2/08 AT25DF641 [Preliminary] Asserted for more details on protection State Type Low Input - ...
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... GROUND: The ground reference for the power supply. GND should be connected to the GND system ground. Figure 2-1. 8-VDFN (Top View (SOI GND 4 AT25DF641 [Preliminary] 4 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be Figure 2-2. VCC 8 HOLD 7 SCK 6 SI (SIO) ...
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... HOLD 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF641 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...
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... Block Erase and Suspend Functions (D8h Command) 64KB 64KB (Sector 127) 64KB 64KB (Sector 126) 64KB 64KB (Sector 0) AT25DF641 [Preliminary] 6 Block Erase Detail 32KB 4KB Block Erase Block Erase Block Address (52h Command) (20h Command) Range 4KB – 000h 4KB – ...
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... All opcode, address, and data bytes are trans- ferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF641 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...
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... Status Register Commands Read Status Register Write Status Register Byte 1 Write Status Register Byte 2 Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down AT25DF641 [Preliminary] 8 Clock Opcode Frequency 1Bh 0001 1011 Up to 100 MHz 0Bh 0000 1011 ...
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... ADDRESS BITS A23-A0 DON'T CARE MSB AT25DF641 [Preliminary] ; however, use of the 1Bh opcode at clock MAX DON'T CARE ...
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... SIO pin. During the next clock cycle, bits 5 and 4 of the first data byte will be output on the SO and SIO pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the last byte (7FFFFFh) of the memory array has been read, AT25DF641 [Preliminary ...
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... HIGH-IMPEDANCE SO 3680B–DFLASH–2/ ADDRESS BITS A23- MSB MSB AT25DF641 [Preliminary OUTPUT OUTPUT DON'T CARE DATA BYTE 1 DATA BYTE ...
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... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. AT25DF641 [Preliminary] 12 “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit only programming a single byte ...
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... MSB ADDRESS BITS A23-A0 DATA IN BYTE MSB MSB AT25DF641 [Preliminary DATA MSB DATA IN BYTE ...
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... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-3. SCK AT25DF641 [Preliminary only programming a single byte “ ...
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... ADDRESS BITS A23- MSB BLKE AT25DF641 [Preliminary INPUT INPUT INPUT DATA BYTE 1 DATA BYTE 2 DATA BYTE ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. AT25DF641 [Preliminary] 16 Block Erase CS 0 ...
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... A program operation is not allowed to a sector that has been erase suspended program operation is attempted to an erase suspended sector, then the program operation will abort and the WEL bit in the Status Register will be reset back to the logical “0” state. Likewise, an erase 3680B–DFLASH–2/08 AT25DF641 [Preliminary] Chip Erase CS 0 ...
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... Protect Sector operation, then the device will simply ignore the opcode and no operation will be performed. The state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE (Sector Lockdown Enabled) bits, will not be affected. AT25DF641 [Preliminary] 18 “Reset” on page 42) is performed while a sector is erase suspended, ...
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... Write Status Register (All Opcodes) Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down 3680B–DFLASH–2/08 AT25DF641 [Preliminary] Operations Allowed and Not Allowed During a Program or Erase Suspend Operation During Operation During Program Suspend Erase Suspend Allowed ...
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... Program/Erase Suspend command must check the status of RES the RDY/BSY bit or the appropriate bit in the Status Register to determine if the previ- ously suspended program or erase operation has resumed. AT25DF641 [Preliminary] 20 Program/Erase Suspend ...
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... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. 3680B–DFLASH–2/08 AT25DF641 [Preliminary] Program/Erase Resume ...
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... Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by AT25DF641 [Preliminary] 22 Write Disable ...
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... WEL bit in the Status Register will be reset to a logical “0”. 3680B–DFLASH–2/08 Protect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF641 [Preliminary ADDRESS BITS A23- MSB Table 9-1 ...
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... Global Protect operation is attempted while a sector is erase or program suspended, the protec- tion operation will abort, the protection states of all sectors in the Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. AT25DF641 [Preliminary] 24 Unprotect Sector ...
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... SPRL bit can be changed back from a 1 since the WP ↕ pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from AT25DF641 [Preliminary] New SPRL Value ...
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... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to AT25DF641 [Preliminary] 26 and Table 11-1 on page 36 , the first byte of data output will not be valid. Therefore, if operat- ...
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... OPCODE ADDRESS BITS A23- MSB MSB HIGH-IMPEDANCE 9-4 and 9-5 detail the various protection and locking states of the device. AT25DF641 [Preliminary DATA BYTE MSB 37 38 ...
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... Table 9-4. (Don't Care) Note: Table 9- AT25DF641 [Preliminary] 28 Sector Protection Register States Sector Protection Register “n” represents a sector number Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from Hardware 1 Locked Locked 0 Can be modified from ...
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... Sector Lockdown Status Sector is not locked down and can be programmed and erased. This is the default state. Sector is permanently locked down and can never be programmed or erased again. 41). To issue the Sector Lockdown command, the CS pin must first be AT25DF641 [Preliminary] “Write Status Reg LOCK ...
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... When the device aborts the Freeze Sector Lockdown State operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. AT25DF641 [Preliminary ...
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... Sector Lockdown Register value is 1 (sector is permanently locked down ADDRESS BITS A23- MSB MSB AT25DF641 [Preliminary ADDRESS BITS A23-A0 CONFIRMATION BYTE ...
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... OTP Security Register locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If less than 64 bytes of data were sent to the device, then the remaining bytes within the OTP Security Register will not AT25DF641 [Preliminary] 32 OTP Security Register ...
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... ADDRESS BITS A23-A0 DATA IN BYTE MSB MSB AT25DF641 [Preliminary not possible to suspend the OTPP time to determine if the data bytes have finished OTPP DATA IN BYTE ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 10-5. Read OTP Security Register SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF641 [Preliminary ADDRESS BITS A23- MSB MSB ...
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... Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. 3680B–DFLASH–2/08 AT25DF641 [Preliminary] , the first two bytes of data output from the Status Register will CLK , at least four bytes of data ...
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... WEL Write Enable Latch Status 0 RDY/BSY Ready/Busy Status Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command. 2. R/W = Readable and writeable R = Readable only AT25DF641 [Preliminary] 36 (2) Type Description 0 Sector Protection Registers are unlocked (default). R/W 1 Sector Protection Registers are locked ...
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... If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or pro- 3680B–DFLASH–2/08 AT25DF641 [Preliminary] (2) Type ...
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... Reset command is disabled and any attempts to reset the device using the Reset command will be ignored. When the RSTE bit is in the logical “1” state, the Reset command is enabled. AT25DF641 [Preliminary] 38 3680B–DFLASH–2/08 ...
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... STATUS REGISTER BYTE MSB MSB AT25DF641 [Preliminary STATUS REGISTER STATUS REGISTER BYTE 2 BYTE MSB ...
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... Byte 1 command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 11-3. Bit 7 SPRL Figure 11-2. Write Status Register Byte 1 AT25DF641 [Preliminary] 40 “Global Protect/Unprotect” on page 24 Write Status Register Byte 1 Format Bit 6 Bit 5 ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. Table 11-4. Bit 7 X Figure 11-3. Write Status Register Byte 2 3680B–DFLASH–2/08 AT25DF641 [Preliminary] Table 11-4). Any additional data bytes that are sent to the device will be Write Status Register Byte 2 Format Bit 6 Bit 5 ...
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... The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. Figure 12-1. Reset AT25DF641 [Preliminary ...
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... Density Code Product Version Code AT25DF641 [Preliminary] Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25DF/26DFxxx series) 48h Density Code: 01000 (64-Mbit) 0 Sub Code: 000 (Standard series) 00h ...
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... The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. AT25DF641 [Preliminary ...
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... If the complete opcode is not clocked in before the CS pin is deasserted the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 12-4. Resume from Deep Power-Down 3680B–DFLASH–2/08 AT25DF641 [Preliminary ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 12-5. Hold Mode CS SCK HOLD AT25DF641 [Preliminary] 46 Hold Hold Hold 3680B–DFLASH–2/08 ...
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... SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DF641 a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH AT25DF641 [Preliminary] 48 *NOTICE: + 0.5V CC Ind. Condition CS, WP, HOLD = all inputs at CMOS levels CS, WP, HOLD = all inputs at CMOS levels f = 100 MHz ...
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... Sector Protect Time (from Chip Select High) SECP (1) t Sector Unprotect Time (from Chip Select High) SECUP (1) t Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High) LOCK 3680B–DFLASH–2/08 AT25DF641 [Preliminary] Min Min 4.3 4.3 0.1 0 ...
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... Not 100% tested (value guaranteed by design and characterization). 14.7 Power-up Conditions Symbol Parameter t Minimum V to Chip Select Low Time VCSL CC t Power-up Device Delay Before Program or Erase Allowed PUW V Power-on Reset Voltage POR AT25DF641 [Preliminary] 50 Min Min Typ 4 Kbytes 32 Kbytes 64 Kbytes Min Max Units 1 µs 30 µs 30 µ ...
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... Input Test Waveforms and Measurement Levels DRIVING LEVELS t R 14.9 Output Test Load 3680B–DFLASH–2/ < (10% to 90%) F DEVICE UNDER TEST 15 pF (frequencies above 70 MHz) or 30pF AT25DF641 [Preliminary MEASUREMENT LEVEL 51 ...
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... Figure 15-2. Serial Output Timing CS SCK Figure 15-3. WP Timing for Write Status Register Byte 1 Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER BYTE 1 OPCODE HIGH-IMPEDANCE SO AT25DF641 [Preliminary CSLH t t CLKH CLKL t DH LSB t CLKH WPH 0 ...
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... Figure 15-4. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI SO 3680B–DFLASH–2/ HHH HLS t HLH t HLS t HLH t t HLQZ AT25DF641 [Preliminary] t HHS t HHS HHQX 53 ...
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... AT25DF641-MWH-T Note: The shipping carrier option code is not marked on the devices. 16S 16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 8MW1 8-contact mm, Very Thin Dual Flat No Lead Package (VDFN) AT25DF641 [Preliminary – – ...
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... The lead width "B", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2325 Orchard Parkway San Jose, CA 95131 R 3680B–DFLASH–2/08 AT25DF641 [Preliminary ...
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... VDFN D Pin TOP VIEW D1 Pin # BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com AT25DF641 [Preliminary Option A Pin #1 Chamfer (C 0.30) Option B e Pin #1 K Notch (0.20 R) TITLE 8MW1, 8-lead ( Body), Thermally Enhanced Plastic Very Thin Dual Flat No Lead ...
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... Revision History Revision Level – Release Date A – December 2007 B – February 2008 3680B–DFLASH–2/08 AT25DF641 [Preliminary] History Initial release. Minor text edits throughout document Changed Standby Current values – Increased typical value from 10 µ µA – Increased maximum value from 20 µ µA Changed minimum Clock High Time and minimum Clock Low Time from 3 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...