tc5565apl-15 TOSHIBA Semiconductor CORPORATION, tc5565apl-15 Datasheet
tc5565apl-15
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tc5565apl-15 Summary of contents
Page 1
... CE2 Chip Enable Inputs I/O1 – I/O8 Data Input/Output V Power (+5V) DD GND Ground N.C. No Connection TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Package Type - (Slim Package) * See TC5563APL Technical Data. (TOP VIEW) Directly TTL Compatible Inputs and Outputs : All Pin Compatible with 2764 type EPROM ...
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... Operating Temperature opr * -3.0V at pulse width 50ns MAX. **Flat package D.C RECOMMENDED OPERATING CONDITIONS SYMBOL V Power Supply Voltage DD V Input High Voltage IH V Input Low Voltage IL V Data-Retention Supply Voltage DH TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 CE2 \ ITEM ...
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... CE2 >= V – 0.2V or CE2 <= 0.2V. DD CAPACITANCE (Ta=25 °C ) SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT * This parameter periodically sampled is not 100% tested. TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 °C TEST CONDITION V O~V IN= DD VOH-2-4V VOL-0. CE2-VOL or IH \CE1 = V or CE2 ...
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... ODW r R/W to Output Low-Z OEW t Data Set up Time DS t Data Hold Time DH A.C. TEST CONDITION Output Load Input Pulse Level Timing Measurement V Reference Level TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 ° 5V±10%) DD TC5565APL-10 TC5565AFL-10 MIN. 100 - - - - TC5565APL-10 TC5565AFL-10 MIN ...
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... TIMING WAVEFORMS READ CYCLE (1) WRITE CYCLE 1 (4) (R/W Controlled Write) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 ...
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... WRITE CYCLE 2 (4) (\CE1 Controlled Write) WRITE CYCLE 3 (4) (CE2 Controlled Write) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 ...
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... Data Retention Supply Voltage DH Stand by Supply Current I DDS2 t Chip Deselection to Data Retention Mode CDR t Recovery Mode R Note (1) : Read cycle Time. \CE1 Controlled Data Retention Mode (2) CE2 Controlled Data Retention Mode (4) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Ta=0~70 °C) PARAMETER VDD=3.0V VDD=5.5V MIN. TYP. MAX. UNIT 2.0 - 5.5 V ...
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... Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient. Therefore the peak current flows only after row address change, as shown in the following figure. This peak current may induce the noise on V recommended to eliminate such noise. TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 current flows during the period that the V DDS1 /GND lines ...
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... Lead pitch is 2.54 and tolerance is +\-0.25 against theoretical center of each lead that is obtained on the basis of No.1 and No.28 leads. MFP 28 PIN OUTLINE DRAWING (F28GC-P) Note) Lead pitch is 1.27 and tolerance is +\-0.12 against theoretical center of each lead that is obtained on the basis of No.1 and N0.28 leads TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Unit in mm Unit in mm ...