at45db021b ATMEL Corporation, at45db021b Datasheet
at45db021b
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at45db021b Summary of contents
Page 1
... To allow for simple in-system reprogrammability, the AT45DB021B does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB021B is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... Pin Configurations and Pinouts Table 2-1. Pin Name CS SCK RESET RDY/BUSY Figure 2-1. Figure 2-3. Note: AT45DB021B 2 Pin Configurations Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy TSOP Top View, Type 1 RDY/BUSY 1 RESET 2 WP ...
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... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB021B is divided into three levels of granularity comprised of sectors, blocks and pages. The Memory Architecture Diagram illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...
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... When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. AT45DB021B 4 9 and 11). A valid Table 5-3 on page 9 1937J– ...
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... If bit then the device busy state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level 1937J–DFLSH–9/05 Status Register Format Bit 6 Bit 5 Bit 4 COMP 0 1 AT45DB021B Bit 3 Bit 2 Bit 1 Bit CAR X ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB021B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen different density configurations ...
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... AT45DB021B PA4 PA3 PA2 PA1 • • • • • • • • ...
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... AT45DB021B 8 ), the status register will indicate that the part is busy. On completion of the com- XFR . During this time, the status register will indicate that the ...
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... Inactive Clock Polarity Low or High SPI Mode Inactive Clock Polarity Low or High SPI Mode Inactive Clock Polarity Low or High SPI Mode Inactive Clock Polarity Low or High SPI Mode AT45DB021B Opcode 68H E8H 52H D2H 54H D4H 56H ...
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... Auto Page Rewrite through Buffer 1 Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB021B 10 SCK Mode Opcode Any ...
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... N/A N AT45DB021B Address Byte ...
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... CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge sampling the inactive clock state. After power is applied and V before an operational mode is started. AT45DB021B the minimum datasheet value, the system should wait ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB021B 0°C to 70°C -40°C to 85°C 2.7V to 3.6V Min Typ Max ...
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... Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC 8.3 Input Test Waveforms and Measurement Levels < (10 8.4 Output Test Load AT45DB021B 14 Min 22 22 250 250 250 2. 2.0 DRIVING MEASUREMENT 0.8 LEVELS LEVEL 0 ...
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... CSS WH SCK t V HIGH IMPEDANCE VALID CSS WL WH SCK HIGH Z SO VALID OUT VALID IN AT45DB021B CSH DIS HIGH IMPEDANCE VALID OUT CSH t DIS HIGH IMPEDANCE H 15 ...
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... It is recommended that “r” logical “0” for densities of 2M bits or smaller. 3. For densities larger than 2M bits, the “r” bits become the most significant Page Address bit for the appropriate density. AT45DB021B 16 SI ...
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... PA6-0, BFA8 BFA7 X···X, BFA8 BFA7-0 n Starts self-timed erase/program operation CMD PA9-7 PA6-0, X AT45DB021B PAGE PROGRAM BUFFER 2 TO PAGE PROGRAM BUFFER 2 (256 BYTES) BUFFER 2 WRITE SI · Completes writing into selected buffer · Starts self-timed erase/program operation n+1 Last Byte · ...
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... Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer 11.3 Buffer Read Each transition represents 8 bits and 8 clock cycles AT45DB021B 18 FLASH MEMORY ARRAY PAGE (264 BYTES) MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (264 BYTES) BUFFER 1 READ I/O INTERFACE PA6-0, BA8 ...
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... DATA OUT HIGH-IMPEDANCE AT45DB021B LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT ...
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... Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE 12.4 Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO AT45DB021B HIGH-IMPEDANCE ...
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... DATA OUT HIGH-IMPEDANCE HIGH-IMPEDANCE AT45DB021B LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB ...
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... Detailed Bit-level Read Timing – SPI Mode 0 14.1 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO 14.2 Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB021B ...
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... HIGH-IMPEDANCE DATA OUT AT45DB021B DATA OUT MSB STATUS REGISTER OUTPUT MSB ...
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... SO 15.3 Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE 15.4 Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO AT45DB021B HIGH-IMPEDANCE HIGH-IMPEDANCE ...
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... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 1937J–DFLSH–9/05 START provide address and data THROUGH BUFFER (82H, 85H) END AT45DB021B BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) 25 ...
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... AN-4 (“Using Atmel’s Serial DataFlash”) for more details. 16. Sector Addressing PA9 PA8 PA7 AT45DB021B 26 START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ...
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... Plastic Thin Small Outline Package (TSOP) 1937J–DFLSH–9/05 Ordering Code AT45DB021B-CC AT45DB021B-RC AT45DB021B-SC AT45DB021B-TC AT45DB021B-CI AT45DB021B-RI AT45DB021B-SI AT45DB021B-TI Ordering Code AT45DB021B-CU AT45DB021B-RU AT45DB021B-SU AT45DB021B-TU Package Type AT45DB021B Package Operation Range 9C1 28R Commercial 8S2 (0°C to 70°C) 28T 9C1 ...
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... Packaging Information 18.1 9C1 – CBGA Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 1.00 (0.0394) BSC NON-ACCUMULATIVE NON-ACCUMULATIVE 2325 Orchard Parkway San Jose, CA 95131 R AT45DB021B 28 5.10(0.201) 4.90(0.193 5.10(0.201) 4.90(0.193) TOP VIEW 1.20(0.047)MAX 2.0 (0.079) 1.50(0.059) REF 1.00 (0.0394) BSC BOTTOM VIEW TITLE 9C1, 9-ball ( Array ...
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... Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 1937J–DFLSH–9/ TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) AT45DB021B COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 2.39 – 2.79 A1 0.050 – 0.356 D 18 ...
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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB021B ∅ End View ...
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... Orchard Parkway San Jose, CA 95131 R 1937J–DFLSH–9/05 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) AT45DB021B 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel istered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...