lm26001bmhx National Semiconductor Corporation, lm26001bmhx Datasheet - Page 15

• Manufacturer Part Number: lm26001bmhx
• Description: 1.5a Switching Regulator With High Efficiency Sleep Mode
• Manufacturer: National Semiconductor Corporation

Design Information
4. A second pole (fpc1) can also be placed at fz. This pole
can be created with a single capacitor, C9. The minimum
value for this capacitor can be calculated by:
C9 may not be necessary in all applications. However if the
operating frequency is being synchronized below the nomi-
nal frequency, C9 is recommended. Although it is not re-
quired for stability, C9 is very helpful in suppressing noise.
A phase lead capacitor can also be added to increase the
phase and gain margins. The phase lead capacitor is most
helpful for high input voltage applications or when synchro-
nizing to a frequency greater than nominal. This capacitor,
shown as C10 in Figure 10, should be placed in parallel with
the top feedback resistor, R1. C10 introduces an additional
zero and pole to the compensation network. These frequen-
cies can be calculated as shown below:
A phase lead capacitor will boost loop phase around the
region of the zero frequency, fzff. fzff should placed some-
what below the fpz1 frequency set by C9. However, if C10 is
too large, it will have no effect.
PCB Layout
Good board layout is critical for switching regulators such as
the LM26001. First, the ground plane area must be sufficient
for thermal dissipation purposes, and second, appropriate
guidelines must be followed to reduce the effects of switch-
ing noise.
Switch mode converters are very fast switching devices. In
such devices, the rapid increase of input current combined
with parasitic trace inductance generates unwanted Ldi/dt
noise spikes at the SW node and also at the VIN node. The
magnitude of this noise tends to increase as the output
current increases. This parasitic spike noise may turn into
electromagnetic interference (EMI), and can also cause
problems in device performance. Therefore, care must be
taken in layout to minimize the effect of this switching noise.
The current sensing circuit in current mode devices can be
easily effected by switching noise. This noise can cause duty
cycle jitter which leads to increased spectral noise. Although
the LM26001 has 100ns blanking time at the beginning of
every cycle to ignore this noise, some noise may remain
after the blanking time. Following the important guidelines
below will help minimize switching noise and its effect on
current sensing.
The switch node area should be as small as possible. The
catch diode, input capacitors, and output capacitors should
be grounded to a large ground plane, with the bulk input
capacitor grounded as close as possible to the catch diode
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15
anode. Additionally, the ground area between the catch di-
ode and bulk input capacitor is very noisy and should be
somewhat isolated from the rest of the ground plane.
A ceramic input capacitor must be connected as close as
possible to the VIN pin and grounded close to the GND pin.
Often this capacitor is most easily located on the bottom side
of the pcb. If placement close to the GND pin is not practical,
the ceramic input capacitor can also be grounded close to
the catch diode ground. The above layout recommendations
are illustrated below in Figure 11.
It is a good practice to connect the EP, GND pin, and small
signal components (COMP, FB, FREQ) to a separate ground
plane, shown in Figure 11 as EP GND, and in the schematics
as a signal ground symbol. Both the exposed pad and the
GND pin must be connected to ground. This quieter plane
should be connected to the high current ground plane at a
quiet location, preferably near the Vout ground as shown by
the dashed line in Figure 11.
The EP GND plane should be made as large as possible,
since it is also used for thermal dissipation. Several vias can
be placed directly below the EP to increase heat flow to other
layers when they are available. The recommended via hole
diameter is 0.3mm.
The trace from the FB pin to the resistor divider should be
short and the entire feedback trace must be kept away from
the inductor and switch node. See Application Note AN-1229
for more information regarding PCB layout for switching
regulators.
Thermal Considerations and TSD
Although the LM26001 has a built in current limit, at ambient
temperatures above 80˚C, device temperature rise may limit
the actual maximum load current. Therefore, temperature
rise must be taken into consideration to determine the maxi-
mum allowable load current.
Temperature rise is a function of the power dissipation within
the device. The following equations can be used to calculate
power dissipation (PD) and temperature rise, where total PD
is the sum of FET switching losses, FET DC losses, drive
losses, Iq, and VBIAS losses:
PD
TOTAL
FIGURE 11. Example PCB Layout
= Psw
AC
+ Psw
DC
+ PQG + P
Iq
20179449
+ P
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VBIAS