lt3011emse Linear Technology Corporation, lt3011emse Datasheet - Page 10

• Manufacturer Part Number: lt3011emse
• Description: 50ma, 3v To 80v Low Dropout Micropower Linear Regulator With Pwrgd
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LT3011
in a small package, but they tend to have strong voltage
and temperature coeffi cients, as shown in Figures 2 and 3.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is avail-
able in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be signifi cant enough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verifi ed.
Voltage and temperature coeffi cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress, simi-
lar to the way piezoelectric accelerometer or microphone
works. For a ceramic capacitor, the stress can be induced
by vibrations in the system or thermal transients.
10
Figure 2. Ceramic Capacitor DC Bias Characteristics
–100
–20
–40
–60
–80
20
0
0
2
4
DC BIAS VOLTAGE (V)
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10 F
6
8
X5R
Y5V
10
12
14
3011 F02
16
PWRGD Flag and Timing Capacitor Delay
The PWRGD fl ag is used to indicate that the ADJ pin volt-
age is within 10% of the regulated voltage. The PWRGD
pin is an open-collector output, capable of sinking 50μA
of current when the ADJ pin voltage is low. There is no
internal pull-up on the PWRGD pin; an external pull-up
resistor must be used. When the ADJ pin rises to within
10% of its fi nal reference value, a delay timer is started.
At the end of this delay, programmed by the value of the
capacitor on the C
impedance and is pulled up to a logic level by an external
pull-up resistor.
To calculate the capacitor value on the C
following formula:
Figure 4 shows a block diagram of the PWRGD circuit. At
start-up, the timing capacitor is discharged and the PWRGD
pin will be held low. As the output voltage increases and
the ADJ pin crosses the 90% threshold, the JK fl ipfl op is
reset, and the 3μA current source begins to charge the
timing capacitor. Once the voltage on the C
the V
capacitor voltage is clamped and the PWRGD pin is set to
a high impedance state.
C
Figure 3. Ceramic Capacitor Temperature Characteristics
TIME
CT(HIGH)
=
–100
–20
–40
–60
–80
V
40
20
threshold (approximately 1.7V at 25°C), the
0
CT HIGH
–50
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10 F
(
I
T
CT
–25
pin, the PWRGD pin switches to a high
•
)
t
−
0
DELAY
TEMPERATURE ( C)
V
CT LOW
25
(
50
X5R
Y5V
)
75
100
3011 F03
T
T
125
pin, use the
pin reaches
3011f