hpc36164 National Semiconductor Corporation, hpc36164 Datasheet - Page 7

• Manufacturer Part Number: hpc36164
• Description: High-performance Microcontroller With A/d
• Manufacturer: National Semiconductor Corporation

30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5 ) V
to
Note C
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 t
edge occurs later t
input
Note 4 WS (t
one wait state programmed
Note 5 Due to emulation restrictions actual limits will be better
Note 6 This is guaranteed by design and not tested
a
125 C for HPC16164 HPC16104
CKIR
L
HAE
e
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DC1ALER
DC1ALEF
DC2ALER
DC2ALEF
LL
ST
VP
ARR
ACC
RD
RW
DR
RDA
ARW
WW
V
HW
DAR
RWP
and t
40 pF
is specified for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
Symbol and Formula
WAIT
e
e
e
e
(Continued)
e
e
e
e
e
e
CKIL
e
e
e
)
e
e
HAE
c
t
t
t
t
) on CKI input less than 2 5 ns
C
C
C
(number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency t
t
C
t
t
t
t
C
e
C
may be as long as (3 t
e
C
t
t
C
C
t
a
C
b
a
C
t
t
C
t
b
C
C
b
b
C
a
b
a
b
a
15
b
WS
WS
a
b
9
7
5
15
WS
t
WS
10
t
WS
C
C
5
WS
5
b
b
a
a
b
b
b
32
5
b
20
20
39
14
15
50
C
a
Delay from CKI Rising Edge to
ALE Rising Edge
Delay from CKI Rising Edge to
ALE Falling Edge
Delay from CK2 Rising Edge to
ALE Rising Edge
Delay from CK2 Falling Edge to
ALE Falling Edge
ALE Pulse Width
Setup of Address Valid before
ALE Falling Edge
Hold of Address Valid after
ALE Falling Edge
ALE Falling Edge to RD Falling Edge
Data Input Valid after Address Output Valid
Data Input Valid after RD Falling Edge
RD Pulse Width
Hold of Data Input Valid after
RD Rising Edge
Bus Enable after RD Rising Edge
ALE Falling Edge to WR Falling Edge
WR Pulse Width
Data Output Valid before WR Rising Edge
Hold of Data Valid after WR Rising Edge
Falling Edge of ALE to
Falling Edge of RDY
RDY Pulse Width
4WS
a
72 t
C
a
CC
100) may occur depending on the following CPU instruction cycles its wait states and ready
Parameter
e
5V
7
g
10% T
A
e
0 C to
a
70 C for HPC46164 HPC46104
Min
101
24
11
11
85
51
28
94
66
0
0
9
0
7
Max
100
35
35
37
37
60
35
33
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
e
(Notes 1 2)
(Notes 1 2)
30 MHz with
(Note 2)
(Note 2)
(Note 6)
Notes
b
55 C