lm27212 National Semiconductor Corporation, lm27212 Datasheet - Page 14

• Manufacturer Part Number: lm27212
• Description: Two-phase Current-mode Hysteretic Buck Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
Design Considerations
In the equations, τ is the delay from error comparator trip
point to the instant external power FETs start to switch. For
the LM27212 and LM27222, that value is found to be 150ns
typical.
To determine the maximum switching frequency, first use the
following equation to find the V
peaks (notice that maximum switching frequency happens at
maximum V
Then calculate the frequency using V
V
Example: RR1 = RR2, Re = 3mΩ, L = 0.6µH, maximum V
= 1.356V, maximum V
= 3mΩ, Rds1 = 10mΩ, Rds2 = 4mΩ, I
= 100µA, RH1 = 40Ω.
So V
f
Lowest switching frequency happens at minimum V
maximum V
So for the above example, f
OUTPUT CAPACITORS
Output capacitors are critical in controlling the output voltage
excursion when a load transient first happens. The initial
voltage excursion consists of two portions, that caused by
the output capacitor ESR, and that caused by the total
capacitance. When the ESR value is close to the load line
slope value, the initial voltage excursion will be dominated by
the ESR. Otherwise, it will be mainly caused by loss of
charge in the capacitors. For a load transient tutorial, please
refer to the Output Capacitor Selection section in the
LM2633 datasheet.
It is apparent that the ESR should not exceed the load line
slope |r|, or the load device’s specification will immediately
be violated. In addition, the output capacitance should be
greater than a minimum value which is required by the
worst-case unloading transient.
where
Example 1: L = 0.6µH, ∆I
r = -3mΩ, δ = 10mV, V
The calculated ∆V
max
out_max
= 350kHz
in_fmax
for V
out
in
= 6.83V and maximum switching frequency is
.
out
value.):
.
c_s
V
out
= 64mV
in
rip
= 8.4V, minimum V
c_s
= V
= 12mV.
= 20A, R
min
ref
+ I
in
= 250kHz.
value where the frequency
out
e
x r
= 3mΩ, V
out
in_fmax
(Continued)
= 0A, r = -3mΩ, ih
out
= 0.84V, RS1
out
for V
= 1.356V,
in
out
, and
and
out
14
The calculated minimum output capacitance is C
1026µF.
Example 2: L = 0.2µH, ∆I
1.00V, r = -3mΩ, δ = 10mV, V
The calculated ∆V
The calculated minimum output capacitance is C
The above calculations are based on the assumption that
when the worst-case unloading transient happens, the top
FETs of the two channels immediately turn off. If that is not
always the case, more capacitance is needed and a bench
test is probably necessary to determine how much more is
needed.
OUTPUT INDUCTOR SELECTION
Large output inductor values will need large output capacitor
values, whereas smaller inductance will cause larger output
ripple voltage. To meet the budget for output ripple voltage,
we need to find out what the ripple current in the inductors is.
We know the peak-to-peak inductor current is:
By plotting switching frequency curves, it is found that the
largest ripple current happens at the highest V
Example: RR1 = RR2, R
= 1.356V, maximum V
R
The calculated frequency is f = 266kHz, and D = 0.09
So the peak-to-peak inductor current is ∆i = 7.73A
Therefore the output peak-to-peak ripple voltage is 23.2mV.
MOSFET SELECTION
Bottom FET Selection
During normal operation, the bottom FET is turned on and off
at almost zero voltage. So only conduction loss is present in
the bottom FET. The bottom FET power loss peaks at the
maximum input voltage and load current. The most important
parameter when choosing the bottom FET is the on-
resistance. The lower the on-resistance, the less the power
loss. The equation for the maximum allowed on-resistance at
room temperature for a given FET package, is:
where T
in the FET, T
R
and TC is the temperature coefficient of the on-resistance
which is typically 4000ppm/˚C.
If the calculated on-resistance is smaller than the lowest
value available, multiple FETs can be used in parallel. If the
design criterion is to use the highest R
R
current. In the case of two FETs in parallel, multiply the
ds2
θja
ds2_max
is the junction-to-ambient thermal resistance of the FET,
= 4mΩ, I
j_max
of a single FET can be increased due to reduced
is the maximum allowed junction temperature
a_max
out
= 0A, r = -3mΩ, ih = 100µA, RH1 = 40Ω.
c_s
is the maximum ambient temperature,
= 64mV
in
e
= 15V, RS1 = 3mΩ, R
c_s
= 3mΩ, L = 0.6µH, maximum V
= 20A, R
rip
= 12mV
e
= 0.125mΩ, V
ds
FET, then the
in
ds1
min
and V
= 10mΩ,
= 313µF.
min
out
out
out
.
=
=