lm27213mtd National Semiconductor Corporation, lm27213mtd Datasheet - Page 17

• Manufacturer Part Number: lm27213mtd
• Description: Single Phase Hysteretic Buck Controller
• Manufacturer: National Semiconductor Corporation

Component Selection
A simulation of the above conditions with the addition of 10
pieces of a 22µF ceramic capacitor yields a peak excursion
of 1.180V, which is well within the specified limit.
MOSFET SELECTION
The choice of power FETs is driven primarily by efficiency or
thermal considerations. There are two main loss compo-
nents to consider, conduction losses and switching losses.
The switching losses are primarily due to parasitics in the
FETs and are very hard to estimate with any degree of
accuracy. The conduction losses are much easier to charac-
terize. The switching losses in the synchronous FET are very
low since it’s essentially a zero voltage switched device.
However, the high-side device’s switching losses are usually
comparable to its conduction losses. The primary contributor
to high-side FET switching losses is related to the reverse
recovery characteristics of the synchronous FET’s body di-
ode. During the small dead band where both FETs are off
every cycle, the synchronous FET’s body diode will carry the
inductor current. Problems arise because the body diode
exhibits a significant reverse recovery time, trr. During this
time, the FET looks like a short circuit. When the high-side
FET is subsequently turned on, there is a shoot through path
from the input supply to ground. A larger high-side FET will
tend to exhibit a larger shoot through current. Therefore, it is
undesirable to oversize the high-side device. Since the syn-
chronous FET looks like a short, the entire supply voltage is
impressed across the high-side device, along with a simul-
taneous high current. The result is very high momentary
power dissipation. The total power lost is a direct function of
the switching frequency.
For a single-phase design something on the order of 1W of
dissipation in the power switches is a reasonable place to
start. Assume further that this will be split equally between
the high and low side FETs. Since the low-side FET switches
at nearly zero volts the transition losses will be very low. The
high-side switch will, however, sustain large switching
losses. In all likelihood they will be comparable to, or exceed,
the conduction losses.
With 500mΩ allocated to the synchronous switch dissipation
we can calculate the required on-resistance. Assume the hot
on-resistance will be about 140% of the room temp R
Therefore:
Where: DF = duty factor or V
P
And I is the design thermal current
As a general rule of thumb, assume the design thermal
current is approximately 80% of full load current unless the
specification indicates otherwise. In this case, assume a
current of 9.6A. Also, duty factor should be calculated at high
input line voltage. Assume 16V for our example. So the
maximum on-resistance for the synchronous switch will be:
R
In a similar fashion the high-side switch can be sized. Allot
of the total dissipation to switching losses. The on interval is
now DF rather than 1-DF and low input line is assumed:
R
diss
ds(on)
ds(on)
= allowed dissipation
= 4.2mΩ
= 13.4mΩ
R
ds(on)
R
ds(on)
R
R
= 0.5W/(9.6A
ds(on)
ds(on)
= 0.25W/(9.6A
= P
= P
diss
diss
/(I
2
/(I
out
2
x 1.4 x (1-1.15V/16V))
2
2
x 1.4 x (1-DF))
/V
x 1.4 x (DF))
x 1.4 x 1.15V/8V)
in
(Continued)
ds(on)
1
⁄
2
.
17
An Si7390 high-side switch and an Si7336 low-side switch
meet this requirement
If the same analysis is done assuming a 12A continuous load
current the results suggest a low-side FET with an on-
resistance of 2.7mΩ and a high-side FET on-resistance of
8.6mΩ.
GATE DRIVE REQUIREMENTS
The bootstrap capacitor choice is based largely on the gate
charge requirements of the high-side FET. The charge
stored on the bootstrap cap should be about 20X the high-
side FET’s gate charge. For the Si7390 the specified gate
charge is 15nC max. So the bootstrap capacitor should store
a minimum of 300nC at 5V. This translates to a capacitance
of 0.06µF or larger. A 0.10µF or larger X5R dielectric capaci-
tor would be a good choice. Under sizing the bootstrap
capacitor will result in inadequate gate drive to the high-side
switch.
INPUT CAPACITOR SELECTION
The input capacitor selection is based largely on ripple cur-
rent capability. The instantaneous pulse currents drawn by
the power supply must be deliv-ered by the input capacitors.
This is related to the fact that the input power source, be it a
battery pack or a wall adapter, will place a substantial im-
pedance in series with the input path. As such, their ability to
deliver large, fast rise time current pulses is limited. The
input capacitors need to average these pulse currents and
smooth the current demand placed on the source.
Ceramic capacitors offer a good combination of ripple cur-
rent capability and voltage rating, however they tend to do so
with relatively low capacitance values. It’s also not uncom-
mon to find wall adapters and batteries with impedances on
the order of several hundred milliohms. The result is that
while cycle-by-cycle current demand may be met, the input
capacitor network cannot deliver enough energy to prevent
significant amounts of voltage ripple when the load current is
varied at a low rate. In particular, if the load varies at a
frequency in the 2kHz to 4kHz range, the resulting large
variation in voltage observed at the power supply input will
result in noticeable audio noise being produced by the piezo
electric effects that are characteristic of ceramic capacitors.
There are several ways to mitigate this problem. The first is
to use physically small ceramic capacitors since they tend to
be less efficient noise generators. That, however, would tend
to limit the amount of capacitance to an unacceptably low
value. The use of aluminum-poly type capacitors such as
Sanyo’s Poscap series is a viable option as well. They can
provide adequate levels of capacitance with very good ripple
current capability. The down side of this solution is cost.
Another possible approach is to use relatively large ceramic
capacitors and add a relatively large aluminum electrolytic
capacitor to hold up the supply voltage. The ceramics deliver
the high frequency pulse currents while the bulk caps
smooth the longer term variation. In general a few hundred
microfarads is adequate for this purpose. As long as the AC
ripple voltage impressed on the ceramic capacitors is small,
on the order of a few tenths of a volt, the ceramic capacitors
are not going to be excessively noisy.
For purposes of sizing the high frequency input decoupling,
the RMS input ripple current must be estimated. The input
ripple current will be approximately 50% of the output current
at a 50% duty factor and decrease as duty factor drops.
Figure 5 shows this relationship.
www.national.com