a4984 Allegro MicroSystems, Inc., a4984 Datasheet
a4984
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a4984 Summary of contents
Page 1
... It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. Step modes are selectable by MSx logic inputs. It has an output drive capacity and ±2 A. The A4984 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. ...
Page 2
... DMOS Microstepping Driver with Translator undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4984 is supplied in three surface mount packages: two QFN packages, the 4 mm × 4 mm, 0.75 mm nominal overall height ES package, and the 5 mm × × 0. package. The LP package is a 24-pin TSSOP. All three packages have exposed pads for enhanced thermal dissipation, and are lead (Pb) free (suffix – ...
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... A4984 VREG VDD Current Regulator REF DAC PWM Latch Blanking Mixed Decay STEP DIR RESET Translator Control MS1 Logic MS2 PWM Latch ENABLE Blanking Mixed Decay SLEEP DAC V REF DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 F CP1 ROSC Charge OSC ...
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... A4984 ELECTRICAL CHARACTERISTICS Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis Blank Time ...
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... A4984 THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Package Thermal Resistance *In still air. Additional thermal information available on Allegro Web site. DMOS Microstepping Driver with Translator Test Conditions* ES package; estimated, on 4-layer PCB, based on JEDEC standard R ET package; estimated, on 4-layer PCB, based on JEDEC standard θ ...
Page 6
... A4984 STEP MSx RESET, or DIR STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table DMOS Microstepping Driver with Translator ...
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... Functional Description according to the ROSC configuration and the step sequence, as shown in figures 8 through 11. During Mixed decay, when the trip point is reached, the A4984 initially goes into a fast decay mode for 31.25% of the off-time, t decay mode for the remainder of t feature appears on the next page. ...
Page 8
... A4984 Slow Mixed Decay Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. Figure 2. Missed steps in low-speed microstepping I 500 mA/div. LOAD Step input 10 V/div. Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded) DMOS Microstepping Driver with Translator and Overcurrent Protection ...
Page 9
... FET outputs. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. V monitored. In the case of a fault condition, the FET outputs of the A4984 are disabled. and Overcurrent Protection This function blanks the output of the current sense (μs), is approximately ...
Page 10
... FETs, current regulator, and charge pump. A logic low on the S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ pin puts the A4984 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4984 drives the motor to the Home microstep position) ...
Page 11
... A4984 V STEP 100.00 70.71 I OUT 0 –70.71 –100.00 I OUT Symbol I Figure 7. Current Decay Modes Timing Chart DMOS Microstepping Driver with Translator See Enlargement A Enlargement PEAK Characteristic t Device fixed off-time off Maximum output current PEAK t Slow decay interval SD t Fast decay interval ...
Page 12
... For optimum electrical and thermal performance, the A4984 must be soldered directly onto the board. On the under- side of the A4984 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB ...
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... VDD DMOS Microstepping Driver with Translator OUT2B C6 GND OUT2A R4 R5 OUT1A GND OUT1B BULK GND CAPACITANCE C2 VBB LP package typical application and circuit layout and Overcurrent Protection A4984 GND CP1 C3 ENABLE CP2 OUT2B VCP C4 VBB2 PAD VREG SENSE2 C5 MS1 OUT2A MS2 OUT1A ...
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... A4984 VDD VBB 8 V GND GND V BB VREG SENSE 10 V GND DMOS Microstepping Driver with Translator Pin Circuit Diagrams GND PGND GND MSx DIR V REG VREF ROSC DMOS SLEEP Parasitic GND and Overcurrent Protection VCP CP1 CP2 GND GND ...
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... A4984 STEP 100.00 70.71 Phase 1 I OUT1A 0.00 Direction = H (%) –70.71 –100.00 100.00 70.71 Phase 2 I OUT2A 0.00 Direction = H (%) –70.71 –100.00 Figure 8. Decay Mode for Full-Step Increments STEP Phase 1 I OUT1A Direction = H (%) –100.00 Phase 2 I OUT2B Direction = H (%) –100.00 Figure 10. Decay Modes for Quarter-Step Increments DMOS Microstepping Driver with Translator ...
Page 16
... A4984 STEP 100.00 92.39 83.15 70.71 55.56 38.27 Phase 1 19.51 I OUT1A 0.00 Direction = H –19.51 (%) –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 38.27 Phase 2 19.51 I OUT2B 0.00 Direction = H –19.51 (%) –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 Figure 11. Decay Modes for Eighth-Step Increments DMOS Microstepping Driver with Translator Mixed* Slow Mixed Mixed* ...
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... A4984 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Phase 1 Full Half 1/4 1/8 Current Step Step Step Step [% I tripMax ] # # # # DMOS Microstepping Driver with Translator ...
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... A4984 ES Package OUT2B 1 18 ENABLE 2 17 GND 3 16 PAD CP1 4 15 CP2 5 14 VCP 6 13 Terminal List Table Name ES CP1 4 CP2 5 DIR 17 ¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ 2 GND 3, 16 MS1 8 MS2 9 NC – OUT1A ...
Page 19
... A4984 ES Package, 24-Pin QFN with Exposed Thermal Pad 4.00 ±0. 25X 0.08 C +0.05 0.25 –0.07 0.50 BSC 0.45 MAX DMOS Microstepping Driver with Translator 4.00 ±0.15 C SEATING PLANE 0.75 ±0.05 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal # 2.70 D 2.70 and Overcurrent Protection 0.30 0. 2.70 2.70 4.10 C PCB Layout Reference View For Reference Only ...
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... A4984 ET Package, 32-Contact QFN with Exposed Thermal Pad 33X 0.08 C 0.25±0.10 0.50±0. DMOS Microstepping Driver with Translator 5.00 ±0. 5.00 ±0.15 C SEATING PLANE 0.90 ±0.10 C 0.50 BSC For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-6) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 3 ...
Page 21
... A4984 LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0. 4.32 24X 0.10 C +0.05 0.25 0.65 –0.06 Copyright ©2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products ...