a4982 Allegro MicroSystems, Inc., a4982 Datasheet
a4982
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a4982 Summary of contents
Page 1
... There are no phase sequence tables, high frequency control lines, or complex interfaces to program. Approximate size The A4982 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. During stepping operation, the chopping control in the A4982 automatically selects the current decay mode, Slow or Mixed. ...
Page 2
... DMOS Microstepping Driver with Translator undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4982 is supplied in two surface mount package, the ET × 5 mm, 0.90 mm nominal overall package height QFN package, and the LP package, a 24-pin TSSOP. Both packages have exposed pads for enhanced thermal dissipation, and are lead (Pb) free (suffix – ...
Page 3
... A4982 VREG VDD Current Regulator REF DAC PWM Latch Blanking Mixed Decay STEP DIR RESET Control Translator MS1 Logic MS2 PWM Latch ENABLE Blanking Mixed Decay SLEEP DAC V REF DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 F CP1 ROSC Charge OSC ...
Page 4
... A4982 ELECTRICAL CHARACTERISTICS Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis Blank Time ...
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... A4982 THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Package Thermal Resistance *In still air. Additional thermal information available on Allegro Web site. DMOS Microstepping Driver with Translator Test Conditions* ET package; estimated, on 4-layer PCB, based on JEDEC standard R θJA LP package; on 4-layer PCB, based on JEDEC standard Maximum Power Dissipation ...
Page 6
... A4982 STEP MS1, MS2, RESET, or DIR STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table DMOS Microstepping Driver with Translator ...
Page 7
... A4982 The A4982 is a complete microstepping Device Operation. motor driver with a built-in translator for easy operation with minimal control lines designed to operate bipolar step- per motors in full-, half-, quarter-, and sixteenth-step resolution modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry ...
Page 8
... A4982 Slow Mixed Decay Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. Figure 2. Missed steps in low-speed microstepping I 500 mA/div. LOAD Step input 10 V/div. Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded) DMOS Microstepping Driver with Translator and Overcurrent Protection ...
Page 9
... E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ input state. Shutdown undervoltage (on VCP), the FET outputs of the A4982 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state ...
Page 10
... FETs, current regulator, and charge pump. A logic low on the S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ pin puts the A4982 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4982 drives the motor to the Home microstep position) ...
Page 11
... A4982 V STEP 100.00 70.71 I OUT 0 –70.71 –100.00 I OUT Symbol I Figure 7. Current Decay Modes Timing Chart DMOS Microstepping Driver with Translator See Enlargement A Enlargement PEAK Characteristic t Device fixed off-time off Maximum output current PEAK t Slow decay interval SD t Fast decay interval ...
Page 12
... For optimum electrical and thermal performance, the A4982 must be soldered directly onto the board. On the underside of the A4982 package is an exposed pad, which provides a path for enhanced thermal dissipa- tion. The thermal pad should be soldered directly to an exposed surface on the PCB ...
Page 13
... DMOS RESET Parasitic SLEEP GND and Overcurrent Protection OUT2B OUT2A OUT1A OUT2B OUT1B VBB2 VBB1 C6 PAD ENABLE DIR GND GND CP1 A4982 REF CP2 STEP ROSC VCP CP1 CP2 GND GND GND V BB DMOS Parasitic 8 V GND GND GND Allegro MicroSystems, Inc ...
Page 14
... A4982 STEP 100.00 70.71 Phase 1 I OUT1A 0.00 Direction = H (%) –70.71 –100.00 100.00 70.71 Phase 2 I OUT2A 0.00 Direction = H (%) –70.71 –100.00 Figure 10. Decay Mode for Full-Step Increments STEP Phase 1 I OUT1A Direction = H (%) –100.00 Phase 2 I OUT2B Direction = H (%) –100.00 Figure 12. Decay Modes for Quarter-Step Increments DMOS Microstepping Driver with Translator ...
Page 15
... A4982 STEP 100 Phase OUT1A Direction = H 0 (%) –10 –20 –29 –38 –47 –56 –63 –71 –77 –83 –88 –96 –100 100 Phase OUT2B Direction = H 0 (%) –10 –20 –29 – ...
Page 16
... A4982 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Half 1/4 1/16 Phase 2 Step Step Step Step Current (#) (#) (#) (#) (% I TRIP(max 18.75 4 29. 37.50 6 46.88 7 56.25 8 64. 70.31 10 76.56 11 82.81 12 87. 92.19 14 95.31 15 98.44 16 100. 100.00 18 100.00 19 98.44 20 95. 92.19 22 87.50 23 82.81 24 76. ...
Page 17
... A4982 ET Package OUT2B VBB2 ENABLE 5 GND 6 CP1 7 CP2 8 Terminal List Table Name CP1 CP2 DIR ¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯ GND MS1 MS2 2, 4, 21, NC 23, 26, 28, 29, 31 OUT1A OUT1B OUT2A OUT2B REF ¯ ...
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... A4982 ET Package, 32-Contact QFN with Exposed Thermal Pad 33X 0.08 C 0.25±0.10 0.50±0. DMOS Microstepping Driver with Translator 5.00 ±0. 5.00 ±0.15 C SEATING PLANE 0.90 ±0.10 C 0.50 BSC For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-6) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 3 ...
Page 19
... A4982 LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0. 4.32 24X 0.10 C +0.05 0.25 0.65 –0.06 Copyright ©2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products ...