a4986 Allegro MicroSystems, Inc., a4986 Datasheet
a4986
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a4986 Summary of contents
Page 1
... Special power-up sequencing is not required. The A4986 is supplied in a 24-pin TSSOP (LP) with exposed thermal pad for enhanced thermal performance. It has a 0.65 pitch and an overall package height of ≤1.2 mm lead (Pb) free, with 100% matte tin leadframe plating. ...
Page 2
... A4986 Selection Guide Part Number A4986SLPTR-T 24-pin TSSOP with exposed thermal pad Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Input Voltage Logic Supply Voltage VBBx to OUTx Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature DMOS Dual Full-Bridge PWM Motor Driver Package 4000 pieces per 13-in ...
Page 3
... A4986 REGULATOR VREG 0.22 μF Sense2 DAC PWM Latch OSC V BLANKING REF Mixed Decay VDD IN01 IN02 PH1 CONTROL LOGIC IN11 IN12 PH2 SLEEP PWM Latch BLANKING Mixed Decay REF V REF DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection Functional Block Diagram 0.1 μ ...
Page 4
... A4986 ELECTRICAL CHARACTERISTICS Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Logic Input Pull-down Logic Input Hysteresis Blank Time ...
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... A4986 THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Package Thermal Resistance *In still air. Additional thermal information available on Allegro Web site. DMOS Dual Full-Bridge PWM Motor Driver Symbol Test Conditions package; on 4-layer PCB, based on JEDEC standard θJA Maximum Power Dissipation ...
Page 6
... A4986 The A4986 is designed to operate one Device Operation. stepper motor in full, half, or quarter step mode. The currents in each of the output full-bridges, all N-channel DMOS, are regu- lated with fixed off-time pulse width modulated (PWM) control circuitry. Each full-bridge peak current is set by the value of ...
Page 7
... FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A4986 into Sleep mode. When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay before issu- ing a logic command ...
Page 8
... A4986 V STEP 100.00 70.71 I OUT 0 –70.71 –100.00 I OUT Symbol I Figure 4. Current Decay Modes Timing Chart DMOS Dual Full-Bridge PWM Motor Driver See Enlargement A Enlargement PEAK Characteristic t Device fixed off-time off Maximum output current PEAK t Slow decay interval SD t Fast decay interval ...
Page 9
... For optimum electrical and thermal performance, the A4986 must be soldered directly onto the board. On the under- side of the A4986 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB ...
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... A4986 VDD VBB 8 V GND GND V BB VREG SENSE 10 V GND DMOS Dual Full-Bridge PWM Motor Driver Pin Circuit Diagrams GND PGND GND IN01 IN02 IN11 IN12 V REG PH1 PH2 DMOS VREF Parasitic ROSC SLEEP GND with Overcurrent Protection VCP ...
Page 11
... A4986 100.0 66.7 Phase 1 0 (%) –66.7 –100.0 100.0 66.7 Phase 2 0 (%) –66.7 –100.0 Full step 2 phase Modified full step 2 phase Figure 5. Step Sequencing for Full-Step Increments. DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection Step Sequencing Diagrams 100.0 66.7 Phase 1 0 (%) –66.7 –100.0 100 ...
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... A4986 100.0 66.7 33.3 Phase 1 0 (%) –33.3 –66.7 –100.0 100.0 66.7 33.3 Phase 2 0 (%) –33.3 –66.7 –100.0 Step Sequencing Settings Full 1 Denotes modified step mode DMOS Dual Full-Bridge PWM Motor Driver Figure 7. Step Sequence for Quarter-Step Increments Phase 1 1/4 I0x ...
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... A4986 Terminal List Table Name CP1 CP2 PH1 PH2 GND IN02 IN12 NC OUT1A OUT1B OUT2A OUT2B REF IN11 ROSC SENSE1 SENSE2 ¯ S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ IN01 VBB1 VBB2 VCP VDD VREG PAD *The GND pins must be tied together externally by connecting to the PAD ground plane under the device ...
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... A4986 LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0. 4.32 24X 0.10 C +0.05 0.25 0.65 –0.06 Copyright ©2009-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products ...