tc94a04af TOSHIBA Semiconductor CORPORATION, tc94a04af Datasheet
tc94a04af
Available stocks
Related parts for tc94a04af
tc94a04af Summary of contents
Page 1
... TC94A04AF/AFD is a single-chip audio Digital Signal Processor, incorporating 4 way stereo analog switch converter converter, and electronic volume for trimming possible to realize many applications, such as sound field control -hall simulation, for example-, digital filter for equalizers, surround, base boost and something. ...
Page 2
Ω Ω Ω Ω Ω Ω Ω Ω Σ∆ Σ∆ Ω Ω ...
Page 3
Ω Ω Ω Ω Ω Ω Ω Ω Σ∆ Σ∆ Ω Ω ...
Page 4
...
Page 5
...
Page 6
...
Page 7
...
Page 8
... When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AF/AFD loads the IFDI signal on the IFCK signal rising edge. When CS = “H”, the IFCK and IFDI signals are don’t care. ...
Page 9
The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field ...
Page 10
... In ACMP mode, the TC94A04AF/AFD does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example signal flow filter is designed as in the following diagram, unless the data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data ...
Page 11
... C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AF/AFD loads the IFDI data on the IFCK signal rising edge. When CS = “H”, IFCK and IFD signal are don't care. → ...
Page 12
The RAMs are set by command data using the IFDI signal. 2 The first byte after the I C address (32h command, which differs for each RAM. The next two bytes contain the start address for each ...
Page 13
... In ACMP mode, the TC94A04AF/AFD does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example signal flow filter is designed as in the following diagram, unless the data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data ...
Page 14
The following table lists the control commands that can be used from the microcontroller. = µ = ...
Page 15
Each command explanation is shown below. *mark in each command explanation table shows the initial value at the time of reset. * ...
Page 16
...
Page 17
* * ← ← ← ...
Page 18
...
Page 19
Data are sent continuously after transmitting the module sequence RAM head address (2 bytes). Enable a sequential write to RAM. 45h-MSEQ RAM address (2 bytes)-data (2 bytes)-data (2 bytes)- (module sequential RAM: 8 words) ...
Page 20
The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 46h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)- (CRAM: 384 words) -data (2 bytes) K ...
Page 21
It is CRAM write-in command which used the address compare mode. A maximum of 32 words is written at once. The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to ...
Page 22
It is ORAM write-in command which used the address compare mode. The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 48h-ORAM address (2 bytes)-data (2 bytes)-data (2 ...
Page 23
The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 49h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)- (ORAM: 16 words) -data ...
Page 24
− − − * − − − ...
Page 25
− − − * − − − = −∞ = × − − − − ...
Page 26
...
Page 27
... The TC94A04AF/AFD supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later. The microcontroller interface circuit supports two format: I mode. However, the boot must be executed in Standard Transmission. × ...
Page 28
The following shows the breakdown of the 18 bits. = ...
Page 29
Self-boot operation supports two modes: one for use at reset and for setting the microcontroller. To enter this mode, set the RST pin to High or send initialized command. The 2048 fs period (46.4 ms when fs = 44.1 kHz) ...
Page 30
After a power-supply injection, once at least, please set up a required register after applying reset which makes RST terminal “L” level and making the value of an internal register decide. In rewriting coefficient data and offset data using ACMP ...
Page 31
= = = = − − − − = − = = − ...
Page 32
× × = = − = − − = = = × × µ ...
Page 33
+ + + + + → → → → Ω − ...
Page 34
− = = = = µ ...
Page 35
Standard transmission mode ( CS , IFCK, IFDI, IFDO) ↓ ↓ ↑ ↑ ↑ ↑ ↓ = µ ( mode ( CS , IFCK, IFDI) ...
Page 36
Clock pin (XI) (2) Reset (3) Audio serial interface (ELRI/O, EBCI/O, DIN0 to 2, DOUT) ∼ ...
Page 37
Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO) 2 (5) Microcontroller interface mode (IFCK, IFDI) 2 Purchase of Toshiba I C components conveys a license under the Philips I 2 these components ...
Page 38
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ µ µ µ µ µ µ ...
Page 39
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ µ µ µ µ µ µ ...
Page 40
...
Page 41
...
Page 42
• • • • • ...