tc94a09f TOSHIBA Semiconductor CORPORATION, tc94a09f Datasheet - Page 5

• Manufacturer Part Number: tc94a09f
• Description: Single-chip Cd Processor With Built-in Controller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Pin Descriptions
Number
100
1~9
Pin
97
98
99
10
11
12
13
14
15
16
17
18
COM1/OT1
COM2/OT2
COM3/OT3
COM4/OT4
S10/OT14
S11/OT15
S12/OT16
S13/OT17
S14/OT18
P8-0/S15
P8-1/S16
P8-2/S17
P8-3/S18
S9/OT13
S1/OT4
Symbol
/MBOV
/AOUT
/ZDET
/CLCK
/DATA
/SFSY
/LRCK
/BCK
/IPF
~
/LCD segment output
LCD common output
LCD segment output
LCD segment output
/output port
/output port
/output port
/CD signal
/CD signal
Pin Name
I/O port
Common signal output pins for the LCD panel.
Those pins configure matrix with S1 to S18 and
display up to 72 segments.
The LCD can be driven by the 1/2 or 1/3 bias
method. When the 1/2 bias method is set three
levels, MV
at 2-ms intervals. When the 1/3 bias method is
set four levels, MV
GND, are output at a 62.5 Hz cycle (when
either the 4.5 MHz or 75 kHz crystal oscillator is
used).
After system reset or clock stop execution is
released, the non-selected waveform (bias
voltage) is output. The DISP OFF bit is set to 0
and the common signal is output.
These pins can be switched to an output port
(Note1) or LED driver pins by program. They
are usually used for digit output to drive the
LEDs.
Segment signal output pins for the LCD panel.
Those pins configure a matrix with COM1 to
COM4 and display up to 72 segments.
When the 1/2 bias method is set two levels,
MV
method is set four levels, MV
2/3MV
The S1 to S14 pins can be switched to an
output port (Note1) by program. Port 8 and S15
to S18 pins can be switched pin by pin to an I/O
port and segment output pins. When the pins
are set to an I/O port, output is N-channel open
drain.
The S10 to S14 and P8-0 to P8-3 pins can be
switched to CD signal input/output pins by
program. Setting the CD10 bit to 1 switches the
pins to the LRCK, BCK, and AOUT pins as the
CD pins in batches. The other pins can be
individually switched according to the
S14/S15/S16 segment data.
/CLCK Inputs/outputs sub code P to W data
/DATA Outputs sub code P to W data.
/SFSY
/LRCK Outputs channel clock (44.1 kHz).
/BCK
/AOUT Outputs audio data.
/MBOV Outputs buffer-memory-overflow
/IPF
/ZDET
Pins set as an output port are used for segment
output for the LED driver. The output port can
increment OT1 to OT18 by instruction,
facilitating access to data in external RAM and
ROM.
(Note1) After a system reset, pins also used as
DD
DD
and GND, are output. When the 1/3 bias
output ports are set to LCD output;
pins also used as I/O ports are set to
I/O port input.
, and GND, are output.
reading clock.
Outputs frame sync signal for
playback.
When L channel, outputs Low. When
R channel, outputs High. The polarity
can be inverted by command.
Outputs bit clock (1.4112 MHz).
signal. When buffer memory
overflows, outputs H.
Outputs interpolation pointing flag. If
AOUT output is C2 error
detection/correction, outputs High to
indicate correction is impossible.
Outputs 1-bit DAC zero detection flag.
DD
Function and Operation
, 1/2MV
5
DD
DD
, 1/3MV
, and GND, are output
DD
DD
, 1/3MV
, 2/3MV
DD
DD
,
, and
Input
instruction
MV
DD
MV
Remarks
DD
TC94A09F
MV
MV
2001-10-15
DD
DD
Bias
potential
Bias
voltage
MV
DD