tc94a29fag TOSHIBA Semiconductor CORPORATION, tc94a29fag Datasheet - Page 6

• Manufacturer Part Number: tc94a29fag
• Description: Single-chip Cd Processor With Built-in Controller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

No.
Pin
52
53
54
55
56
57
58
59
60
61
62
63
P2-0/COM1
P2-1/COM2
P2-2/COM3
P2-3/COM4
/P3-0/S1
P3-1/S2
P3-2/S3
P3-3/S4
P4-0/S5
P4-1/S6
P4-2/S7
P4-3/S8
Symbol
TEST
/LCD common output
/LCD segment output
/LCD segment output
/LCD segment output
/I/O port 3-0
Pin Name
Test input
I/O port 2
I/O port 3
I/O port 4
24-bit CMOS I/O port and 3-bit N-channel
open-drain I/O port.
Input/output can be specified for each bit. When
the P6-0 to P6-3 pins are used as I/O port input,
each pin can be pulled up or down by program.
When the P5-1 (BRK3) to P7-2 (BRK16) pins
are used as I/O port input and backup release
for clock stop mode or wait mode is enabled for
those pins (enabled/disabled in port units), a
change in any of the pins can release the
backup state. The P7-0 to P7-2 pins constitute
an N-channel open-drain I/O port, to which a
voltage of up to 5.5 V can be applied.
I/O ports 2 to 6 can be set to LCD driver output
pins by program. The COM1 to COM4 pins
drive common signals to the LCD panel while
the S1 to S16 pins drive segment signals. The
COM1 to COM4 signals configure a matrix with
the S1 to S16 signals to display up to 64
segments.
When the LCDoff bit is set to 0, the COM1 to
COM4 and S1 to S4 pins are collectively set to
LCD output. For S5 to S16, the program can
specify either I/O port or segment output
individually for each pin.
The LCD can be driven by the 1/4-duty, 1/2-bias
method (frame frequency: 62.5 Hz) or the
1/4-duty, 1/3-bias method (frame frequency: 125
Hz). When the 1/2 bias method is set, three
common output levels (MVDD, 1/2MVDD and
GND) and two segment output levels (MVDD
and GND) appear on the pins. When the 1/3
bias method is set, four common and segment
output levels (MVDD, 1/3MVDD, 2/3MVDD and
GND) appear on the pins.
Upon a system reset or after clock stop mode is
released, a non-select waveform (bias voltage)
is driven and the DISP OFF bit is set to 0, after
which the common signals are driven.
During a system reset ( RESET = low), the
TEST/P3-0/S1 pin is pulled down and accepts
test mode input. This pin should be left open or
applied low level during a reset.
The P5-1 to P6-3 and P1-0 to P1-2 pins can be
set to CD processor-dedicated pins on a per pin
basis. The CD processor functions are as
follows:
Function and Operation
6
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instruction
instruction
instruction
TC94A29FAG/FB
Input
Input
Input
R
IN2
Remarks
MV
2003-04-01
Reset signal
SS
MV
MV
MV
LCD
voltage
LCD
voltage
LCD
voltage
MV
MV
MV
DD
DD
DD
DD
DD
DD