attiny11 ATMEL Corporation, attiny11 Datasheet - Page 16

• Manufacturer Part Number: attiny11
• Description: 8-bit Microcontroller With 1k Byte Flash
• Manufacturer: ATMEL Corporation

Memory Access and
Instruction Execution
Timing
16
ATtiny11/12
Register Operands Fetch
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 14 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 14. The Parallel Instruction Fetches and Instruction Executions
Figure shows the internal timing concept for the register file. In a single clock cycle, an
ALU operation using two register operands is executed and the result is stored back to
the destination register.
Single-cycle ALU Operation
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
System Clock Ø
System Clock Ø
T1
T1
T2
T2
T3
T3
1006F–AVR–06/07
T4
T4