atxmega256a3b-mu ATMEL Corporation, atxmega256a3b-mu Datasheet
atxmega256a3b-mu
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atxmega256a3b-mu Summary of contents
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... Building control Motor control • • Board control Networking • • White Goods Optical 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications 8/16-bit XMEGA A3B Microcontroller ATxmega256A3B Preliminary 8116C–AVR–02/09 ...
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... Ordering Code Flash ATxmega256A3B-AU 256 ATxmega256A3B-MU 256 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green ...
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Overview The XMEGA microcontrollers based on the AVR instructions in a single clock cycle, the XMEGA A3B achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con- sumption versus processing ...
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The XMEGA A3B devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 3.1 Block Diagram Figure 3-1. XMEGA A3B Block Diagram PA[0..7] PORT A (8) ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA A Manual • XMEGA A Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth. ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in SRAM • Stack Pointer accessible in I/O memory space • Direct ...
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The program memory is In- System Self-Programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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... Since all AVR instructions are 16- or 32-bits wide, each Flash Flash Program Memory (Hexadecimal address) 0 Application Section (256 KB) ... 1EFFF 1F000 Application Table Section (8 KB) 1FFFF 20000 Boot Section (8 KB) 20FFF Figure 7-2 on page Data Memory Map (Hexadecimal address) ATxmega256A3B 0 I/O Registers (4 KB) FFF XMEGA A3B 9. To simplify development, the memory map for 9 ...
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Figure 7-2. 7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 ...
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Production Signature Row The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify ...
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... Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions. 8116C–AVR–02/09 Table 7-1 on page .Device ID bytes for XMEGA A3B device. Device Byte 2 ATxmega256A3B XMEGA A3B 12. The serial number consist of Device ID bytes Byte ...
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... Table 7-3. Devices EEPROM Size ATxmega256A3B 4 KB 8116C–AVR–02/09 shows the Flash Program Memory organization. Flash write and erase Number of words and Pages in the Flash. ...
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DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...
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Event System 9.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • Events can be ...
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Figure 9-1. The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com- munication Module (IRCOM). Events can also be generated from software (CPU). All ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...
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Figure 10-1. Clock system overview Internal Oscillator Calibrated Internal Run-Time Calibrated Internal Oscillator Run-time Calibrated Internal Oscillator Each clock source is briefly described in the following sub-sections. 10.3 Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 ...
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Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 ...
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Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A3B provides various ...
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Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals ...
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System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – JTAG Reset – PDI reset – Software reset • Asynchronous ...
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JTAG reset The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details. 12.3.6 PDI reset ...
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Battery Backup System 13.1 Features • Battery Backup voltage supply from dedicated V – One Ultra Low-power 32-bit Real Time Counter – One 32.768 kHz crystal oscillator with failure detection monitor – Two Backup Registers • Typical power consumption ...
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Figure 13-1. Battery Backup Module and its power domain implementation VBAT V BAT power supervisor XOSC monitor TOSC1 XOSC TOSC2 RTC Backup Registers 8116C–AVR–02/09 Power Watchdog w/ switch independent RCOSC OCD & Programming Interface Peripherals Internal RAM XMEGA A3B Main ...
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PMIC - Programmable Multi-level Interrupt Controller 14.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x048 ACB_INT_base 0x04E ADCB_INT_base 0x056 PORTE_INT_base 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x06A TCE1_INT_base 0x074 USARTE0_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base 0x08E ADCA_INT_base 0x09A TCD0_INT_base ...
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I/O Ports 15.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...
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Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) 15.3.4 Bus-keeper The bus-keeper’s weak output produces the ...
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down Figure 15-6. I/O configuration - Wired-AND with optional pull-up 8116C–AVR–02/09 DIRn OUTn INn OUTn INn INn OUTn XMEGA A3B Pn Pn ...
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Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...
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T/C - 16-bit Timer/Counter with PWM 16.1 Features • Seven 16-bit Timer/Counters – Four Timer/Counters of type 0 – Three Timer/Counters of type 1 • Four Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture ...
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...
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AWEX - Advanced Waveform Extension 17.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...
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Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 18.2 Overview ...
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RTC32 - 32-bit Real-Time Counter 19.1 Features • 32-bit resolution • One 32-bit Compare register • One 32-bit Period register • Clear Timer on overflow • Optional Interrupt/ Event on overflow and compare match • Selectable clock reference – ...
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TWI - Two Wire Interface 20.1 Features • Two Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space ...
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SPI - Serial Peripheral Interface 21.1 Features • Two Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...
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USART 22.1 Features • Six Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...
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IRCOM - IR Communication Module 23.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...
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Crypto Engine 24.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • ...
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ADC - 12-bit Analog to Digital Converter 25.1 Features • Two ADCs with 12-bit resolution • 2 Msps sample rate for each ADC • Signed and Unsigned conversions • 4 result registers with individual input channel control for each ...
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Figure 25-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results ...
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DAC - 12-bit Digital to Analog Converter 26.1 Features • One DAC with 12-bit resolution • Msps conversion rate for each DAC • Flexible conversion range • Multiple trigger sources • 1 continuous output or 2 ...
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AC - Analog Comparator 27.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on ...
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Figure 27-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8116C–AVR–02/09 XMEGA A3B + Pin 0 output AC0 - Interrupts Interrupt sensitivity control + AC1 ...
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Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 27-1 on page ...
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OCD - On-chip Debug 28.1 Features • Complete Program Flow Control – Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor • Debugging on C and high-level language source code level • Debugging on Assembler and disassembler level ...
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Program and Debug Interfaces 29.1 Features • PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) • JTAG Interface (IEEE std. 1149.1 compliant) • Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG) • Access to the OCD ...
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Pinout and Pin Functions The pinout of XMEGA A3B is shown in I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate ...
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XCKn RXDn TXDn SS MOSI MISO SCK 30.1.6 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT 30.1.7 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8116C–AVR–02/09 Transfer Clock for USART n Receiver Data for USART n Transmitter Data for ...
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Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head ...
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Table 30-4. Port D - Alternate functions PORT D PIN # INTERRUPT GND 24 VCC 25 PD0 26 SYNC PD1 27 SYNC PD2 28 SYNC/ASYNC PD3 29 SYNC PD4 30 SYNC PD5 31 SYNC PD6 32 SYNC PD7 33 SYNC ...
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Table 30-7. Port R- Alternate functions PORT R PIN # INTERRUPT PDI 56 PDI_DATA RESET 57 PDI_CLK PRO 58 SYNC PR1 59 SYNC 8116C–AVR–02/09 PDI XMEGA A3B XTAL XTAL2 XTAL1 54 ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A3B. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Base Address 0x0000 0x0010 ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...
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Packaging information 33.1 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...
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D Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA ...
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Electrical Characteristics - TBD 34.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin with respect to Ground..-0. Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ...
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Speed The maximum frequency of the XMEGA A3B devices is depending on V 34-1 on page 63 Figure 34-1. Maximum Frequency vs. Vcc 8116C–AVR–02/09 the Frequency vs. V curve is linear between 1.8V < MHz 32 Safe ...
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ADC Characteristics – TBD Table 34-1. ADC Characteristics Symbol Parameter Resolution Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Conversion Time ADC Clock Frequency DC Supply Voltage Source Impedance Start-up time AVCC Analog Supply Voltage Table 34-2. ...
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DAC Characteristics – TBD Table 34-3. DAC Characteristics Symbol Parameter Resolution Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Calibrated Gain/Offset Error Output Range Output Settling Time Output Capacitance Output Resistance Reference Input Voltage Reference Input Capacitance ...
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Typical Characteristics - TBD 8116C–AVR–02/09 XMEGA A3B 66 ...
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... Errata 36.1 ATxmega256A3B 36.1.1 rev. B • Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously • DAC is nonlinear and inaccurate if the external reference is above 2. • ADC gain stage output range is limited to 2.4V • Sampled BOD in Active mode will cause noise when bandgap is used as reference • ...
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Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 Sampled BOD in Active mode will cause noise ...
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A • Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously • DAC is nonlinear and inaccurate if the external reference is above 2. • ADC gain stage output range ...
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Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 Sampled BOD in Active mode will cause noise when bandgap ...
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Both DFLLs and both oscillators has to be enabled for one to work In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscilla- tors, the DFLL for both oscillators and both oscillators ...
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... Datasheet Revision History 37.1 8116C - 02/09 1. 37.2 8116B - 12/08 1. 37.3 8116A - 11/08 1. 8116C–AVR–02/09 Added ”Errata” on page 67 for ATxmega256A3B rev B. Added ”Errata” on page 67 for ATxmega256A3B rev A. Initial version. XMEGA A3B 72 ...
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Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 2 3 Overview ................................................................................................... 3 4 Resources ................................................................................................. 5 5 Disclaimer ................................................................................................. 5 6 AVR CPU ................................................................................................... 6 7 Memories .................................................................................................. ...
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Power Management and Sleep Modes ................................................. 20 12 System Control and Reset .................................................................... 22 13 Battery Backup System ......................................................................... 24 14 PMIC - Programmable Multi-level Interrupt Controller ....................... 26 15 I/O Ports .................................................................................................. 28 16 T/C - 16-bit Timer/Counter ...
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RTC32 - 32-bit Real-Time Counter ........................................................ 36 20 TWI - Two Wire Interface ....................................................................... 37 21 SPI - Serial Peripheral Interface ............................................................ 38 22 USART ..................................................................................................... 39 23 IRCOM - IR Communication Module .................................................... 40 24 Crypto Engine ........................................................................................ ...
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... Program and Debug Interface ......................................................................49 30.1Alternate Pin Function Description ........................................................................50 30.2Alternate Pin Functions .........................................................................................52 33.164A ........................................................................................................................60 33.264M2 .....................................................................................................................61 34.1Absolute Maximum Ratings* .................................................................................62 34.2DC Characteristics ................................................................................................62 34.3Speed ....................................................................................................................63 34.4ADC Characteristics – TBD ...................................................................................64 34.5DAC Characteristics – TBD ...................................................................................65 34.6Analog Comparator Characteristics – TBD ...........................................................65 36.1ATxmega256A3B ..................................................................................................67 37.18116C - 02/09 ........................................................................................................72 37.28116B - 12/08 ........................................................................................................72 37.38116A - 11/08 ........................................................................................................72 XMEGA A3B iv ...
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