atxmega256a3b-mu ATMEL Corporation, atxmega256a3b-mu Datasheet - Page 23

• Manufacturer Part Number: atxmega256a3b-mu
• Description: 8/16-bit Xmega A3b Microcontroller
• Manufacturer: ATMEL Corporation

12.3.5
12.3.6
12.3.7
12.4
12.4.1
12.4.2
8116C–AVR–02/09
WDT - Watchdog Timer
JTAG reset
PDI reset
Software reset
Features
Overview
The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains
of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details.
The MCU can be reset through the Program and Debug Interface (PDI).
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
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The XMEGA A3B has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-
controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevents microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-
ming a fuse. In Always-on mode, application software can not disable the WDT.
11 selectable timeout periods, from 8 ms to 8s.
Two operation modes
Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
Configuration lock to prevent unwanted changes
– Standard mode
– Window mode
XMEGA A3B
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