c8051t623-g Silicon Laboratories, c8051t623-g Datasheet - Page 197

• Manufacturer Part Number: c8051t623-g
• Description: Full Speed Usb Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T622/3 and C8051T326/7
23.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “ Note that the CPU is stalled during EPROM write operations and USB FIFO MOVX accesses
(see Section “10.2.3. Accessing USB FIFO Space” on page 53). Interrupt service latency will be increased
for interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the
standard interrupt service procedure (as described above) and the amount of time the CPU is stalled.” on
page 61); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section “ Note that the
CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section
“10.2.3. Accessing USB FIFO Space” on page 53). Interrupt service latency will be increased for interrupts
occurring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.” on page 61).
Both counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1 –
T0M0 in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each
operating mode is described below.
23.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4 – TL0.0. The three upper bits of TL0 (TL0.7 – TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“17.3. Priority Crossbar Decoder” on page 100 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 23.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 12.7). Setting
GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see Section “ Note that the
CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section
“10.2.3. Accessing USB FIFO Space” on page 53). Interrupt service latency will be increased for interrupts
occurring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.” on page 61),
facilitating pulse width measurements
204
Note: X = Don't Care
TR0
0
1
1
1
GATE0
X
0
1
1
Rev. 1.1
INT0
X
X
0
1
Counter/Timer
Disabled
Disabled
Enabled
Enabled