cop87l88rd National Semiconductor Corporation, cop87l88rd Datasheet - Page 22

• Manufacturer Part Number: cop87l88rd
• Description: 8-bit Cmos Otp Microcontrollers With 16k Or 32k Memory And 8-channel A/d With Prescaler
• Manufacturer: National Semiconductor Corporation

www.national.com
Note 15: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-
dress of a block. In this case, the table must be in the next block.
Interrupts
VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active inter-
rupt is software trap, than E0 is generated. This number re-
places the lower byte of the PC. The upper byte of the PC re-
mains unchanged. The new PC is therefore pointing to the
(Continued)
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Arbitration
Ranking
Software
Reserved
External
Timer T0
Timer T1
Timer T1
MICROWIRE/PLUS
Reserved
Reserved
Reserved
Timer T2
Timer T2
Timer T3
Timer T3
Port L/Wakeup
Default
Source
TABLE 4. Interupt Vector Table
INTR Instruction
Pin G0 Edge
Underflow
T1A/Underflow
T1B
BUSY Low
T2A/Underflow
T2B
T3A/Underflow
T3B
Port L Edge
VIS Instr. Execution
without Any Interrupts
22
Description
vector of the active interrupt with the highest arbitration rank-
ing. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the
service routine of the active interrupt with the highest arbitra-
tion ranking.
Figure 15 illustrates the different steps performed by the VIS
instruction. Figure 16 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
0yFE–0yFF
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
0yF6–0yF7
0yF4–0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0yEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
Vector (Note 15)
Hi-Low Byte
Address