cop87l88cf National Semiconductor Corporation, cop87l88cf Datasheet - Page 15

• Manufacturer Part Number: cop87l88cf
• Description: 8-bit Cmos Otp Microcontrollers With 16k Memory And A/d Converter
• Manufacturer: National Semiconductor Corporation

Timers
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Power Save Modes
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device is placed in the HALT mode by writing a “1” to the
HALT flag (G7 data bit). All microcontroller activities, includ-
ing the clock, timers, and A/D converter, are stopped. The
WATCHDOG logic is disabled during the HALT mode. How-
ever, the clock monitor circuitry if enabled remains active
and will cause the WATCHDOG output pin (WDOUT) to go
low. If the HALT mode is used and the user does not want to
activate the WDOUT pin, the Clock Monitor should be dis-
abled after the device comes out of reset (resetting the Clock
Monitor control bit with the first write to the WDSVR register).
In the HALT mode, the power requirements of the device are
minimal and the applied voltage (V
V
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second
method is with a low to high transition on the CKO (G7) pin.
This method precludes the use of the crystal clock configura-
tion (since CKO becomes a dedicated output), and so may
be used with an RC clock configuration. The third method of
exiting the HALT mode is by pulling the RESET pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
Mode
r
1
2
3
(V
r
= 2.0V) without altering the state of the machine.
(Continued)
TxC3
1
1
0
0
0
1
0
1
TxC2
0
0
0
0
1
1
1
1
CC
) may be decreased to
TxC1
1
0
0
1
0
0
1
1
PWM: TxA Toggle
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
Captures:
TxA Pos. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Description
15
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the t
clock is derived by dividing the oscillator clock down by a fac-
tor of 10. The Schmitt trigger following the CKI inverter on
the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
If an RC clock option is being used, the fixed delay is intro-
duced optionally. A control bit, CLKDLY, mapped as configu-
ration bit G7, controls whether the delay is to be introduced
or not. The delay is included if CLKDLY is set, and excluded
if CLKDLY is reset. The CLKDLY bit is cleared on reset.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter
and exit the HALT mode as described above. With the HALT
disable mask option, the device cannot be placed in the
HALT mode (writing a “1” to the HALT flag will have no ef-
fect).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled re-
mains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
Autoreload RA
Autoreload RA
Timer
Underflow
Timer
Underflow
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Interrupt A
Source
Autoreload RB
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Pos. TxB Edge
Neg. TxB
Edge
Neg. TxB
Edge
Neg. TxB
Edge
c
Interrupt B
instruction cycle clock. The t
Source
t
Pos. TxA
Edge
Pos. TxA
Edge
t
t
t
t
t
www.national.com
C
C
C
C
C
C
Counts On
Timer
c