cop87l88fh National Semiconductor Corporation, cop87l88fh Datasheet - Page 14

• Manufacturer Part Number: cop87l88fh
• Description: 8-bit Cmos Otp Microcontrollers With 16k Memory, Comparators, Usart And Hardware Multiply/divide
• Manufacturer: National Semiconductor Corporation

www.national.com
Timers
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the in-
put capture mode.
In this mode, the timer Tx is constantly running at the fixed t
rate. The two registers, RxA and RxB, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger con-
dition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag Tx-
ENA allows the interrupt on TxA to be either enabled or dis-
abled. Setting the TxENA flag enables interrupts to be gener-
ated when the selected trigger condition occurs on the TxA
pin. Similarly, the flag TxENB controls the interrupts from the
TxB pin.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Mode
1
2
FIGURE 9. Timer in External Event Counter Mode
(Continued)
TxC3
1
1
0
0
TxC2
0
0
0
0
TxC1
1
0
0
1
DS101135-13
PWM: TxA Toggle
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Description
c
14
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 10 shows a block diagram of the timer in Input Cap-
ture mode.
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3
TxC2
TxC1
TxC0
TxPNDA Timer Interrupt Pending Flag
TxENA
TxPNDB Timer Interrupt Pending Flag
TxENB
FIGURE 10. Timer in Input Capture Mode
Autoreload RA
Autoreload RA
Timer
Underflow
Timer
Underflow
Interrupt A
Source
Timer mode control
Timer mode control
Timer mode control
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
Autoreload RB
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Interrupt B
Source
t
t
Pos. TxA
Edge
Pos. TxA
Edge
C
C
Counts On
Timer
DS101135-14