cop87l84bc National Semiconductor Corporation, cop87l84bc Datasheet
cop87l84bc
Available stocks
Related parts for cop87l84bc
cop87l84bc Summary of contents
Page 1
... COP87L84BC 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface General Description The COP87L84BC OTP (One Time Programmable) micro- controllers are highly integrated COP8 ™ vices with 16k OTP EPROM memory and advanced features including a CAN 2.0B (passive) interface and two Analog comparators ...
Page 2
... Block Diagram Connection Diagrams Note:X = Crystal Oscillator E = Halt Mode Enabled Top View Order Number COP87L84BCM-XE See NS Package Number M28B FIGURE 2. Connection Diagrams www.national.com FIGURE 1. Block Diagram Pinouts for 28-Pin SO Package Port Pin Type Alt. Function G0 I/O INTR G1 I/O G2 I/O T1B G3 I/O T1A G4 I I/O SK ...
Page 3
Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin −0. Electrical Characteristics −40˚C T +85˚C A ...
Page 4
DC Electrical Characteristics −40˚C T +85˚C A Parameter Maximum Input Current without Latchup Room Temp RAM Retention Voltage, V 500 ns Rise and Fall Time r Input Capacitance Load Capacitance on D2 Note 2: Maximum rate of voltage change must ...
Page 5
Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin −0. Electrical Characteristics: −40˚C T +85˚C A ...
Page 6
Comparator DC/AC Characteristics: 4.5V V 5.5V, −55˚C T +125˚ Parameter Input Offset Voltage Input Common Mode Voltage Range Voltage Gain Outputs Sink/Source DC Supply Current (when enabled) Response Time CAN Comparator DC and AC Characteristics: 4.8V V 5.2V, ...
Page 7
Typical Performance Characteristics Port D Source Current DS101137-39 Ports G/L Source Current DS101137-41 Ports G/L Weak Pull-Up Source Current DS101137-43 −55˚C T +125˚C A Port D Sink Current DS101137-40 Port G/L Sink Current DS101137-42 Dynamic ...
Page 8
Typical Performance Characteristics Idle CAN Tx0 Sink Current Pin Descriptions V and GND are the power supply pins. CC CKI is the clock input. The clock can come from a crystal os- cillator (in conjunction ...
Page 9
Pin Descriptions (Continued) isters associated with the G Port, a data register and a con- figuration register. Therefore, each of the 6 I/O bits (G0–G5) can be individually configured under software control. Since input only pin and ...
Page 10
Functional Description Security is an optional feature and can only be asserted after the memory array has been programmed and verified. A se- cured part will read all 00(hex programmer. The part will fail Blank Check and will ...
Page 11
Oscillator Circuits (Continued) DS101137-7 FIGURE 7. Crystal Oscillator Diagram CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crys- tal (or resonator) controlled oscillator. Table 1 shows the component values required for various standard crystal values. ...
Page 12
Timers (Continued) while the pin T1B is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor ...
Page 13
Timers (Continued) The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, T1C3, T1C2 and T1C1, allow the trigger events to be speci- fied either as a positive or a ...
Page 14
Timers (Continued) TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent PWM and ...
Page 15
Timers (Continued) FIGURE 12. PWM Timer Capture Mode Block Diagram FIGURE 13. PWM Timer PWM Mode Block Diagram PWM Control Register (PWMCON)(Address X’00A2) Reserved ESEL PWPND PWIE PWMD PWON Bit 7 The PWMCON Register Bits are: Reserved This bit is ...
Page 16
Timers (Continued) a fixed, non-programmable repetition rate of 255 PWM clock cycles. The timer is clocked by the output of an 8-bit, pro- grammable prescaler, which is clocked with the chip’s CKI frequency. Thus the PWM signal frequency can be ...
Page 17
Timers (Continued) comes greater than RLON, the PWPND bit in the PWM con- trol register is set to “1”. If the PWIE bit is also set to “1”, the PWPND bit is enabled to request an interrupt. It should be ...
Page 18
Power Save Modes (Continued) T0, are stopped. The power supply requirements of the mi- crocontroller in this mode of operation are typically around 30% of normal power requirement of the microcontroller. As with the HALT mode, the device can be ...
Page 19
Multi-Input Wake Up (Continued) FIGURE 16. Multi-Input Wake Up Logic CAN RECEIVE WAKE UP The CAN Receive Wake Up source is always enabled and is always active on a falling edge of the CAN comparator out- put. There is no ...
Page 20
CAN Interface Block (Continued) Fully automatic transmission on error is supported for mes- sages not longer than two bytes. Messages which are longer than two bytes have to be processed by software. The interface is compatible with CAN Specification 2.0 ...
Page 21
Functional Block Description of the CAN Interface (Continued) Transceive Logic (TCL) The TCL is a state machine which incorporates the bit stuff logic and controls the output drivers, CRC logic and the Rx/Tx shift registers. It also controls the synchronization ...
Page 22
Functional Block Description of the CAN Interface In the case of an interrupt driven CAN interface, the calculation of the actual t INT: ; Interrupt latency = 7t<inf>c<reset> µs PUSH A ; 3t<inf>c<reset> µs LD A,AB ...
Page 23
Functional Block Description of the CAN Interface (Continued) This register is read/write. Reserved Bit 7 is reserved and must be zero. RID10..RID4 Receive Identifier bits (upper bits) The RID10...RID4 bits are the upper 7 bits of the eleven bit long ...
Page 24
Functional Block Description of the CAN Interface (Continued) TRANSMIT CONTROL/STATUS (TCNTL) (00BB) NS1 NS0 TERR RERR CEIE Bit 7 NS1..NS0 Node Status, i.e., Error Status. TABLE 6. Node Status NS1 NS0 0 0 Error active 0 1 Error passive 1 ...
Page 25
Functional Block Description of the CAN Interface (Continued) This bit is set when the remote transmission request (RTR) bit in a received frame was set automatically reset through a read of the RXD1 register. To detect RRTR the ...
Page 26
Functional Block Description of the CAN Interface (Continued) ON-CHIP VOLTAGE REFERENCE The on-chip voltage reference is a ratiometric reference. For electrical characteristics of the voltage reference refer to the electrical specifications section. ANALOG SWITCHES Analog switches are used for selecting ...
Page 27
Frame Formats INTRODUCTION There are basically two different types of frames used in the CAN protocol. The data transmission frames are: data/remote frame The control frames are: error/overload frame Note: This device cannot send an overload frame as a result ...
Page 28
Frame Formats (Continued) A remote frame is identical to a data frame, except that the RTR bit is “recessive”, and there is no data field. IDE = Identifier Extension Bit The IDE bit in the standard format is transmitted “dominant”, ...
Page 29
Frame Formats (Continued) START OF FRAME (SOF) The Start of Frame indicates the beginning of data and re- mote frames. It consists of a single “dominant” bit. A node is only allowed to start transmission when the bus is idle. ...
Page 30
Frame Formats (Continued) tive node detecting an error, starts transmitting an active er- ror flag consisting of six “dominant” bits. This causes the de- struction of the actual frame on the bus. The other nodes detect the error flag as ...
Page 31
Frame Formats (Continued) module 1 = error active transmitter detects bit error at t2 module 2 = error active receiver with a local fault at t1 module 3 = error active receiver detects stuff error at t2 FIGURE 27. Error ...
Page 32
Frame Formats (Continued) module 1 = error active receiver with a local fault at t1 module 2 = error passive transmitter detects bit error at t2 module 3 = error passive receiver detects stuff error at t2 FIGURE 28. Error ...
Page 33
Frame Formats (Continued) An error passive unit can participate in bus communication. However, if the unit detects an error it is not allowed to send an active error flag. The unit sends only a passive (“reces- sive”) error flag. A ...
Page 34
Frame Formats (Continued) • An ACK-error occurs in an error passive device and no “dominant” bits are detected while sending the passive error flag. This does not lead to an incrementation of the TEC. • If only one device is ...
Page 35
Frame Formats (Continued) Comparators The device has two differential comparators. Port L is used for the comparators. The output of the comparators is multi- plexed out to two pins. The following are the Port L assign- ments: L6 Comparator 2 ...
Page 36
Comparators (Continued) CMP1EN Enables comparator 1 (“1”=enable). If compara- tor 1 is disabled the associated L-pins can be used as standard I/O. Reserved This bit is reserved and should be zero. The Comparator Select/Control bits are cleared on RESET (the ...
Page 37
Interrupts (Continued) MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of ...
Page 38
Interrupts (Continued) An interrupt service routine typically ends with an RETI in- struction. This instruction sets the GIE bit back to 1, pops the address stored on the stack, and restores that address to the program counter. Program execution then ...
Page 39
Interrupts (Continued) TABLE 9. Interrupt Vector Table Arbitration Source Ranking 1 Software Trap 2 Reserved 3 CAN Receive 4 CAN Error (transmit/receive) 5 CAN Transmit 6 Pin G0 Edge 7 IDLE Timer Underflow 8 Timer T1A/Underflow 9 Timer T1B 10 ...
Page 40
Interrupts (Continued) www.national.com DS101137-30 FIGURE 37. VIS Flowchart 40 ...
Page 41
Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . INT_EXIT: ...
Page 42
Interrupts (Continued) NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag is reset to ...
Page 43
Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of undefined ROM gets zeroes. The opcode for software interrupt is zero. If the program ...
Page 44
MICROWIRE/PLUS (Continued) TABLE 10. MICROWIRE/PLUS Master Mode Clock Selection SL1 SL0 Where t is the instruction cycle clock c MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is ...
Page 45
Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents On-Chip RAM bytes (48 bytes Unused RAM Address Space (Reads As All Ones) 80 ...
Page 46
Addressing Modes (Continued) TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction, with the instruction field being added to the program counter to get the new pro- gram location. JP has a range from −31 ...
Page 47
Instruction Set (Continued) INSTRUCTION SET ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical EXclusive OR IFEQ ...
Page 48
Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration www.national.com [SP] PL, [SP−1] PU,SP−2, PC ...
Page 49
Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the ...
Page 50
NIBBLE LOWER 50 ...
Page 51
Development Tools Support OVERVIEW National is engaged with an international community of inde- pendent 3rd party vendors who provide hardware and soft- ware development tool support. Through National’s interac- tion and guidance, these tools cooperate to form a choice of ...
Page 52
... A full featured, real- time in-circuit emulator for COP8 devices. Includes Met- aLink Windows Debugger, and power supply. Package- specific probes and surface mount adaptors are ordered separately. TOOLS ORDERING NUMBERS FOR THE COP87L84BC FAMILY DEVICES Vendor Tools Order Number National ...
Page 53
Development Tools Support WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Home Office Aisys U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft ...
Page 54
... Physical Dimensions inches (millimeters) unless otherwise noted Order Number COP87L84BC-xxx/M or COP684BC-xxx/M LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1 ...