cop87l42rj National Semiconductor Corporation, cop87l42rj Datasheet - Page 7

• Manufacturer Part Number: cop87l42rj
• Description: 8-bit Cmos Otp Microcontrollers With 4k Or 32k Memory And Comparator
• Manufacturer: National Semiconductor Corporation

Memory
SECURITY FEATURE
The memory array has an associate Security Byte that is lo-
cated outside of the program address range. This byte can
be addressed only from programming mode by a program-
mer tool.
Security is an optional feature and can only be asserted after
the memory arrary has been programmed and verified. A se-
cured part will read all 00(hex) by a programmer. The part
will fail Blank Check and will fail Verify operations. A Read
operation will fill the programmer’s memory with 00(hex).
The Security Byte itself is always readable with value of
00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the in-
struction or indirectly through B, X and SP registers. The de-
vice has 128 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers”, these can be loaded immediately,
decremented and tested. Three specific registers: X, B, and
SP are mapped into this space, the other registers are avail-
able for general usage.
Any bit of data memory can be directly set, reset or tested.
All I/O and registers (except A and PC) are memory mapped;
therefore, I/O bits and register bits can be directly and indi-
vidually set, reset and tested, except the write once only bit
(WDREN, WATCHDOG Reset Enable), and the unused and
read only bits in CNTRL2 and WDREG registers.
Note: RAM contents are undefined upon power-up.
Reset
EXTERNAL RESET
The RESET input pin when pulled low initializes the
micro-controller. The user must insure that the RESET pin is
held low until V
the clock is stabilized. An R/C circuit with a delay 5x greater
than the power supply rise time is recommended ( Figure 4 ).
The device immediately goes into reset state when the RE-
SET input goes low. When the RESET pin goes high the de-
vice comes out of reset state synchronously. The device will
be running within two instruction cycles of the RESET pin go-
ing high. The following actions occur upon reset:
Port L
Port G
Port D
PC
RAM Contents
B, X, SP
PSW, CNTRL1, CNTRL2
and WDREG Reg.
Multi-Input Wakeup Reg.
WKEDG, WKEN
WKPND
(Continued)
CC
is within the specified voltage range and
TRI-STATE
TRI-STATE
HIGH
CLEARED
RANDOM with Power-On-
Reset
UNAFFECTED with external
Reset (power already
applied)
Same as RAM
CLEARED
CLEARED
UNKNOWN
7
The device comes out of the HALT mode when the RESET
pin is pulled low. In this case, the user has to ensure that the
RESET signal is low long enough to allow the oscillator to re-
start. An internal 256 t
with the two pin crystal oscillator. When the device comes
out of the HALT mode through Multi-Input Wakeup, this de-
lay allows the oscillator to stabilize.
The following additional actions occur after the device
comes out of the HALT mode through the RESET pin.
If a two pin crystal/resonator oscillator is being used:
If the external or RC Clock option is being used:
RC
WATCHDOG RESET
With WATCHDOG enabled, the WATCHDOG logic resets
the device if the user program does not service the WATCH-
DOG timer within the selected service window. The WATCH-
DOG reset does not disable the WATCHDOG. Upon
WATCHDOG reset, the WATCHDOG Prescaler/Counter are
each initialized with FF Hex.
The following actions occur upon WATCHDOG reset that are
different from external reset.
WDREN WATCHDOG Reset Enable bit
WDUDF WATCHDOG Underflow bit
Additional initialization actions that occur as a result of
WATCHDOG reset are as follows:
Data and Configuration
Registers for L & G
WATCHDOG Timer
RAM Contents
Timer T1 and A Contents
WATCHDOG Timer Prescaler/Counter
RAM Contents
Timer T1 and A Contents
WATCHDOG Timer Prescaler/Counter
Port L
Port G
Port D
PC
Ram Contents
B, X, SP
PSW, CNTRL1 and CNTRL2
(except
WDUDF Bit) Registers
>
5 x Power Supply Rise Time
FIGURE 4. Recommended Reset Circuit
c
delay is normally used in conjunction
CLEARED
Prescaler/Counter each
loaded with FF
TRI-STATE
TRI-STATE
HIGH
CLEARED
UNCHANGED
UNCHANGED
CLEARED
DS012529-5
UNCHANGED
UNCHANGED
UNKNOWN
ALTERED
UNCHANGED
UNCHANGED
ALTERED
UNCHANGED
www.national.com