cop8cce9imt9 National Semiconductor Corporation, cop8cce9imt9 Datasheet - Page 36

• Manufacturer Part Number: cop8cce9imt9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, 10-bit A/d And Brownout Reset
• Manufacturer: National Semiconductor Corporation

www.national.com
12.0 Timers
output and inverting the PWM duty cycle. If the PWM Timer
is used in low speed mode or if the PWM output toggle is
synchronous with the end of the instruction cycle, this prob-
lem is not seen. The following figure illustrates the PWM
output when the failure is seen. The user should be aware of
the state of Timer T2 before any SBIT or RBIT instructions
are executed which operate on the PORTLD register. If the
PWM output is close to toggling, the user should delay the
SBIT or RBIT instruction. The following program sequence
works to delay the operation. The user may wish to experi-
ment with other sequences to see which best fits the appli-
cation and to make sure that the time between the comple-
tion of the tests and the modification of PORTLD is not too
long.
LD B,#TMR2HI ;POINT B TO THE TIMER
LD A,[B-] ;GET THE VALUE IN THE TIMER
IFGT A,#0 ;IF NON ZERO
JP GOOD ;WE HAVE TIME
WAIT: IFBIT 6,[B] ;TEST BIT 6 OF THE TIMER
JP GOOD ;TIME TO GET IT DONE SAFELY
JP WAIT ;WAIT A WHILE
GOOD: SBIT 2,PORTLD ;GO AHEAD AND SET THE
⇒
The above program uses specific bits of the port for expla-
nation purposes only. The above program uses the SBIT
instruction by way of example. The RBIT instruction will have
the same effect. The above sequence will not work properly
for PWM times shorter than 64 CPU Clock cycles.
12.2.3 Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is clocked by the input signal from the TxA pin after
synchronization to the appropriate internal clock (t
MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1
allow the timer to be clocked either on a positive or negative
edge from the TxA pin. Underflows from the timer are latched
into the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 17 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the
TxA pin is being used as the counter input clock.
BIT
(Continued)
C
or
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12.2.4 Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode. In this mode, the reload registers serve
as independent capture registers, capturing the contents of
the timer when an external event occurs (transition on the
timer input pin). The capture registers can be read while
maintaining count, a feature that lets the user measure
elapsed time and time between events. By saving the timer
value when the external event occurs, the time of the exter-
nal event is recorded. Most microcontrollers have a latency
time because they cannot determine the timer value when
the external event occurs. The capture register eliminates
the latency time, thereby allowing the applications program
to retrieve the timer value stored in the capture register.
In this mode, the timer Tx is constantly running at the fixed t
or MCLK rate. The two registers, RxA and RxB, act as
capture registers. Each register also acts in conjunction with
a pin. The register RxA acts in conjunction with the TxA pin
and the register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin after synchro-
nization to the appropriate internal clock (t
trol bits, TxC3, TxC2 and TxC1, allow the trigger events to be
specified either as a positive or a negative edge. The trigger
condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
FIGURE 17. Timer in External Event Counter Mode
C
or MCLK). Con-
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