cop8ccr9 National Semiconductor Corporation, cop8ccr9 Datasheet
cop8ccr9
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cop8ccr9 Summary of contents
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... Push-Pull Output — Weak Pull Up Input n Schmitt trigger inputs on I/O ports n High Current I/Os n Temperature range: –40˚C to +85˚C and –40˚C to +125˚C (COP8CCR9/CDR9) n Packaging: 44 and 68 PLCC, 44 LLP, 48 and 56 TSSOP n True In-System, real time emulation and debug tools available DS101374 ...
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Block Diagram 4.0 Ordering Information COP8 CB Family and Feature Set Indicator CB = Low Brownout Voltage CC = High Brownout Voltage Brownout www.national.com Part Numbering Scheme Program Program Memory Memory No. Of ...
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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagrams ................................................................................................................................... 6 6.0 Architectural Overview ............................................................................................................................... 10 6.1 EMI REDUCTION .................................................................................................................................... 10 6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...
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TIMER T0 (IDLE TIMER) ...................................................................................................................... 35 12.1.1 ITMR Register .................................................................................................................................. 36 12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 36 12.2.1 Timer Operating Speeds .................................................................................................................. 36 12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 36 12.2.3 Mode 2. ...
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ANALOG INPUT AND SOURCE RESISTANCE CONSIDERATIONS .................................................. 55 16.0 Interrupts .................................................................................................................................................. 56 16.1 INTRODUCTION ................................................................................................................................... 56 16.2 MASKABLE INTERRUPTS ................................................................................................................... 56 16.3 VIS INSTRUCTION ............................................................................................................................... 57 16.3.1 VIS Execution .................................................................................................................................. 58 16.4 NON-MASKABLE INTERRUPT ............................................................................................................ 59 16.4.1 Pending Flag ...
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Connection Diagrams Top View Plastic Chip Package See NS Package Number V68A Top View LLP Package See NS Package Number LQA44A www.national.com Top View Plastic Chip Package 10137402 See NS Package Number V44A 10137455 Top View TSSOP Package See ...
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Connection Diagrams (Continued) 10137457 Top View TSSOP Package See NS Package Number MTD56 7 www.national.com ...
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Connection Diagrams Port Type Alt. Fun L0 I/O MIWU or Low Speed OSC In L1 I/O MIWU or CKX or Low Speed OSC Out L2 I/O MIWU or TDX L3 I/O MIWU or RDX L4 I/O MIWU or T2A ...
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Connection Diagrams Port Type Alt. Fun A5 I/O ADCH5 A6 I/O ADCH6 A7 I/O ADCH7 B0 I/O ADCH8 B1 I/O ADCH9 B2 I/O ADCH10 B3 I/O ADCH11 B4 I/O ADCH12 B5 I/O ADCH13 or A/D MUX OUT B6 I/O ...
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Architectural Overview 6.1 EMI REDUCTION The COP8CBR/CCR/CDR devices incorporate circuitry that guards against electromagnetic interference - an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) ...
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Architectural Overview examples. In many cases, the instruction set can simulta- neously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes exter- nal events and jumps to corresponding service routines ...
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Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC ...
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Electrical Characteristics DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Current Levels D Outputs Source Sink (Note 7) All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) ...
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Electrical Characteristics AC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Timer 1 Input Low Time Timer 2, 3 Input High Time (Note 6) Timer 2, 3 Input Low ...
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Electrical Characteristics A/D Converter Electrical Characteristics (−40˚C ≤ T otherwise noted) (Single-ended mode only) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Conversion Time (including S/H Time) Operating Current Note 9: ...
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Electrical Characteristics DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Current Levels D Outputs Source Sink (Note 7) All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) ...
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Electrical Characteristics AC Electrical Characteristics (−40˚C ≤ T Note 11: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V and outputs driven ...
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Pin Descriptions The COP8CBR/CCR/CDR I/O structure enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be indepen- dently configured as output pin low, output high, input with high impedance or input ...
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Pin Descriptions (Continued) Configuration registers should not be used. All E pins have Schmitt triggers on the inputs. Port E draws no power when unbonded. Port 4-bit I/O Port. All F pins have Schmitt triggers on ...
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Pin Descriptions FIGURE 5. I/O Port Configurations — Input Mode 9.1 EMULATION CONNECTION Connection to the emulation system is made via connector which interrupts the continuity of the RESET, G0, G1, G2 and G3 signals ...
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Functional Description (Continued) The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually ...
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Functional Description 10.4.1 Virtual EEPROM The Flash memory and the User ISP functions (see Section 5.7), provide the user with the capability to use the flash program memory to back up user defined sections of RAM. This effectively provides ...
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Functional Description (Continued) The format of the Option register is as follows: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 WATCH Reserved SECURITY Reserved DOG Bits 7, 6 These bits are reserved and must be ...
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Functional Description (Continued) T2CNTRL: CLEARED T3CNTRL: CLEARED HSTCR: CLEARED ITMR: Cleared except Bit 6 (HSON Accumulator, Timer 1, Timer 2 and Timer 3: RANDOM after RESET WKEN, WKEDG: CLEARED WKPND: RANDOM SP (Stack Pointer): Initialized to RAM ...
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Functional Description One exception to the above is that the brownout circuit will insert a delay of approximately power up or any time the V drops below a voltage of about 1.8V. The device will CC ...
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Functional Description (Continued) FIGURE 11. Reset Circuit Using Power-On Reset 10.8 OSCILLATOR CIRCUITS The device has two crystal oscillators to facilitate low power operation while maintaining throughput when required. Fur- ther information on the use of the two oscillators ...
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Functional Description (Continued) 10.8.2 Clock Doubler This device contains a frequency doubler that doubles the frequency of the oscillator selected to operate the main microcontroller core. The details of how to select either the high speed oscillator or low ...
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Functional Description (Continued) 10.9.6 HSTCR Register (Address X'00AF) Reserved Bit 7 The HSTCR register contains the following bits: T3HS Places Timer T3 in High Speed Mode. T2HS Places Timer T2 in High Speed Mode. 10.9.7 ITMR Register (Address X'00CF) ...
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In-System Programming (Continued) using the MICROWIRE/PLUS ISP routine, the software in the boot ROM will monitor the MICROWIRE/PLUS for com- mands to program the flash memory. When programming the flash program memory is complete, the FLEX bit will have ...
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In-System Programming ...
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In-System Programming (Continued) tools last resort, when this equipment is not available, there is a hardware method to get out of these lockups and force execution from the Boot ROM MICROWIRE/PLUS routine. The customer will then be ...
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In-System Programming Command Function PGMTIM_SET Write Pulse Timing Register PAGE_ERASE Page Erase MASS_ERASE Mass Erase READ_BYTE Read Byte BLOCKR Block Read WRITE_BYTE Write Byte BLOCKW Block Write EXIT EXIT INVALID N/A Note: The user must ensure that Block Writes ...
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In-System Programming Command/ Command Function Label Entry Point cpgerase Page Erase 0x17 cmserase Mass Erase 0x1A creadbf Read Byte 0x11 cblockr Block Read 0x26 cwritebf Write Byte 0x14 cblockw Block Write 0x23 exit EXIT 0x62 uwisp MICROWIRE/ 0x00 PLUS ...
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In-System Programming Register Name ISPADHI High byte of Flash Memory Address ISPADLO Low byte of Flash Memory Address ISPWR The user must store the byte to be written into this register before jumping into the write byte routine. ISPRD ...
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Timers The device contains a very versatile set of timers (T0, T1, T2 and T3). Timers T1, T2 and T3 and associated autoreload/ capture registers power up containing random data. 12.1 TIMER T0 (IDLE TIMER) The device supports applications ...
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Timers (Continued) 12.1.1 ITMR Register CCK LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0 SEL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 7–4: Described in 13.0 Power Saving Features. Note: Documentation for previous COP8 devices, which ...
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Timers (Continued) FIGURE 16. Timer in PWM Mode 12.2.3 Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, Tx, is clocked by ...
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Timers (Continued) FIGURE 18. Timer in Input Capture Mode 12.3 TIMER CONTROL FLAGS The control bits and their functions are summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control in ...
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Power Saving Features (Continued) “mains” by using voltage rectifier and passive components. Low power is demanded even in automotive applications, due to increased vehicle electronics content. This is required to ease the burden from the car battery. Low power ...
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Power Saving Features (Continued) DCEN CCKSEL 0 0 High Speed Mode. Core and Idle Timer Clock = High Speed 1 0 Dual Clock Mode. Core clock = High Speed; Idle Timer = Low Speed 1 1 Low Speed Mode. ...
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Power Saving Features (Continued) Note: To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the instruction in the ap- plication program used for entering the HALT mode should be followed by two consecutive NOP (no-operation) instruc- ...
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Power Saving Features (Continued) IDLE mode. The NOP’s are placed either at the beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode” instruction. For more information on the IDLE Timer and its associated interrupt, ...
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Power Saving Features (Continued) The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state. The IDLE Timer runs continuously at the low speed clock rate, whether or not the ...
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Power Saving Features (Continued) 13.5.2 Low Speed Idle Mode In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the HALT mode. However, the low speed oscillator, IDLE Timer (Timer ...
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Power Saving Features (Continued) 13.6 MULTI-INPUT WAKE-UP The Multi-Input Wake-up feature is used to return (wake-up) the device from either the HALT or IDLE modes. Alternately Multi-Input Wake-up/Interrupt feature may also be used to generate edge ...
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USART (Continued) 14.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 14.2 DESCRIPTION OF USART REGISTER BITS ENU — USART CONTROL AND STATUS REGISTER (Ad- dress at 0BA) ...
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USART (Continued) XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits per frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity. Read/Write, cleared on ...
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USART (Continued) 14.4 USART OPERATION The USART has two modes of operation: asynchronous mode and synchronous mode. 14.4.1 Asynchronous Mode This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to ...
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USART (Continued) 14.6 USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each ...
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USART (Continued) many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive ...
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USART (Continued) Using the above equation can be calculated first 2)/(16 x 19200) = 32.552 Now 32.552 is divided by each Prescaler Factor (Table 18) to obtain ...
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A/D Converter (Continued) 15.1 OPERATING MODES It supports both Single Ended and Differential modes of operation. Two specific analog channel selection modes are supported. These are as follows: 1. Allow any specific channel to be selected at one time. ...
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A/D Converter (Continued) TABLE 21. A/D Converter Channel Selection when the Multiplexor Output is Enabled Select Bits ADCH3 ADCH2 ...
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A/D Converter (Continued) FIGURE 26. A/D with Single Ended Mux Output Feature Enabled FIGURE 27. A/D with Differential Mux Output Feature Enabled 15.1.1.3 Mode Select This 1-bit field is used to select the mode of operation (single ended or ...
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A/D Converter (Continued) 15.2 A/D OPERATION The A/D conversion is completed within fifteen A/D converter clocks. The A/D Converter interface works as follows. Setting the ADBSY bit in the A/D control register ENAD initiates an A/D conversion. The conversion ...
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Interrupts 16.1 INTRODUCTION The device supports fourteen vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer 3, Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input. All interrupts force a branch to location 00FF Hex ...
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Interrupts (Continued) enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its asso- ciated enable and pending bits are set. An interrupt is an asychronous event which may ...
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Interrupts (Continued) The default VIS interrupt vector can be useful for applica- tions in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro- gram context ( etc.) and executing ...
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Interrupts (Continued) 16.4 NON-MASKABLE INTERRUPT 16.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap ...
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Interrupts (Continued SERVICE: RBIT,EXPND,PSW . . . RET I 16.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service ...
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WATCHDOG/Clock Monitor WDSVR WDSVR Bit 7 Bit 17.1 CLOCK MONITOR The Clock Monitor aboard the device can be selected or deselected under program control. The Clock ...
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WATCHDOG/Clock Monitor (Continued) 17.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET. • Following RESET, the ...
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MICROWIRE/PLUS TABLE 30. MICROWIRE/PLUS Master Mode Clock Select SL1 SL0 Where t is the instruction cycle clock C 18.1 MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to ...
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MICROWIRE/PLUS 18.1.2.1 Alternate SK Phase Operation and SK Idle Polarity The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the ...
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MICROWIRE/PLUS FIGURE 35. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High FIGURE 36. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High 19.0 Memory Map All RAM, ports and registers ...
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Memory Map (Continued) Address Contents S/ADD REG xxB8 USART Transmit Buffer (TBUF) xxB9 USART Receive Buffer (RBUF) xxBA USART Control and Status Register (ENU) xxBB USART Receive Control and Status Register (ENUR) xxBC USART Interrupt and Clock Source Register ...
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Instruction Set (Continued) • Sixteen memory mapped registers that allow an opti- mized implementation of certain instructions. • Ability to set, reset, and test any individual bit in data memory address space, including the memory-mapped I/O ports and registers. ...
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Instruction Set (Continued) Indirect from Program Memory. This is a special case of an indirect instruction that allows access to data tables stored in program memory. In the “Load Accumulator Indi- rect” (LAID) instruction, the upper and lower bytes ...
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Instruction Set (Continued) 20.4.1 Arithmetic Instructions The arithmetic instructions perform binary arithmetic such as addition and subtraction, with or without the Carry bit. Add (ADD) Add with Carry (ADC) Subtract with Carry (SUBC) Increment (INC) Decrement (DEC) Decimal Correct ...
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Instruction Set (Continued) Symbols [B] Memory Indirectly Addressed by B Register [X] Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or [B] Meml Direct Addressed Memory or [B] or Immediate Data Symbols Imm ...
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Instruction Set (Continued) 20.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JSRB Addr Jump SubRoutine Boot ROM JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No ...
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Instruction Set (Continued) Register [ (Note 21) 1 (Note 21) 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 21: = Memory location addressed directly. ...
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Nibble Lower 75 www.national.com ...
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... SKFlash, COP8 Emulators, COP8-PM. Eval The ultimate information source for COP8 developers - Integrates with WCOP8 IDE. Organize and manage code, notes, datasheets, etc. Free Online Graphical IDE, featuring UNIS Processor Expert( Code Development Tool with Simulator - Develop applications, simulate and debug, download working code. ...
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Development Support Hardware Emulation and Debug Tools Hardware COP8-EMFlash-00 Emulators COP8-DMFlash-00 COP8-IMFlash-00 Emulator Null COP8-EMFA-68N Target COP8-EMFA-28N Emulator Target COP8-EMFA-44P Package Adapters COP8-EMFA-68P NiceMon Debug COP8-SW-NMON Monitor Utility Development and Production Programming Tools National’s COP8-PM-02 Engineering (Available late 2004) ...
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... WCOP8 IDE and Emulator Debugger, with Assembler/ Linker/ CD-ROM Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation. Included with most tools from National. Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Simulation Expert tool with Graphical and Traditional user interfaces ...
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Development Support Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test. Product COP8Flash COP8 In-Circuit Emulator for Flash Families. Windows based development and Emulators - real-time in-circuit emulation tool, with trace (EM=None; DM/IM=32k), s/w COP8-EMFlash breakpoints (DM=16, ...
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Development Support Vendor Home Office KANDA Systems Unit 17 -18 LTD. Glanyrafon Enterprise Park, Aberystwyth, Ceredigion, SY23 3JQ, UK Tel: +44 1970 621041 Fax: +44 1970 621040 K and K Kaergaardsvej 42 DK-8355 Development ApS Solbjerg Denmark Fax: +45-8692-8500 ...
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... Physical Dimensions Order Number COP8CBR9HLQ8 or COP8CCR9HLQ7 or COP8CDR9HLQ7 inches (millimeters) unless otherwise noted LLP Package (LQA) or COP8CCR9HLQ8 or COP8CDR9HLQ8 NS Package Number LQA44A 81 www.national.com ...
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... Physical Dimensions Order Number COP8CBR9IMT8 or COP8CCR9IMT7 or COP8CDR9IMT7 Order Number COP8CBR9KMT8 or COP8CCR9KMT7 or COP8CCR9KMT8 www.national.com inches (millimeters) unless otherwise noted (Continued) TSSOP Package (MTD) or COP8CCR9IMT8 or COP8CDR9IMTA8 NS Package Number MTD48 TSSOP Package (MTD) or COP8CDR9KMT7 or COP8CDR9KMTA8 NS Package Number MTD56 82 ...
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... Physical Dimensions Order Number COP8CBR9HVA8 or COP8CCR9HVA7 or COP8CCR9HVA8 Order Number COP8CBR9LVA8 or COP8CCR9LVA7 or COP8CCR9LVA8 inches (millimeters) unless otherwise noted (Continued) Plastic Leaded Chip Carrier (VA) or COP8CDR9HVA7 or COP8CDR9HVA8 NS Package Number V44A Plastic Leaded Chip Carrier (VA) or COP8CDR9LVA7 or COP8CDR9LVA8 NS Package Number V68A 83 www.national.com ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...