cop8cde9 National Semiconductor Corporation, cop8cde9 Datasheet - Page 21

• Manufacturer Part Number: cop8cde9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, 10-bit A/d And Brownout Reset
• Manufacturer: National Semiconductor Corporation

4.0 Functional Description
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
T2CNTRL Register (Address X'00C6)
The T2CNTRL register contains the following bits:
HSTCR Register (Address X'00AF)
The HSTCR register contains the following bits:
Bit 7
Bit 7
Bit 7
Unused
T2C3
T1ENA
EXPND External interrupt pending
BUSY
EXEN
GIE
LPEN
T0PND
T0EN
µWPND MICROWIRE/PLUS interrupt pending
µWEN
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
T1ENB
T2C3
T2C2
T2C1
T2C0
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
T2ENA
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
T2ENB
T2HS Places Timer T2 in High Speed Mode.
T2C2
LPEN
Timer T1 Interrupt Enable for Timer Underflow or
T1A Input capture edge
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
L
Wake-up/Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
Enable MICROWIRE/PLUS interrupt
edge
Timer T1 Interrupt Enable for T1B Input capture
edge
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
Timer
modes 1 and 2, Timer T2 Underflow Interrupt
Pending Flag in timer mode 3
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
ture edge
Timer T2 Interrupt Enable for T2B Input capture
edge
T2C1
T0PND
Port
T2
T2C0
Reserved
T0EN
Interrupt
Start/Stop
µWPND
T2PNDA
µWEN
Enable
T2ENA
control
T1PNDB
T2PNDB
(Continued)
(Multi-Input
in
T1ENB
T2ENB
T2HS
timer
Bit 0
Bit 0
Bit 0
21
ITMR Register (Address X'00CF)
The ITMR register contains the following bits:
ENAD Register (Address X'00CB)
The ENAD register contains the following bits:
5.0 In-System Programming
5.1 INTRODUCTION
This device provides the capability to program the program
memory while installed in an application board. This feature
is called In System Programming (ISP). It provides a means
of ISP by using the MICROWIRE/PLUS, or the user can
provide his own, customized ISP routine. The factory in-
stalled ISP uses the MICROWIRE/PLUS port. The user can
provide his own ISP routine that uses any of the capabilities
of the device, such as USART, parallel port, etc.
5.2 FUNCTIONAL DESCRIPTION
The organization of the ISP feature consists of the user flash
program memory, the factory boot ROM, and some registers
dedicated to performing the ISP function. See Figure 13 for
a simplified block diagram. The factory installed ISP that
uses MICROWIRE/PLUS is located in the Boot ROM. The
size of the Boot ROM is 1k bytes and also contains code to
facilitate in system emulation capability. If a user chooses to
write his own ISP routine, it must be located in the flash
program memory.
Bit 7
ADCH3 ADCH2
Bit 7
LSON
LSON
HSON
DCEN
CCKSEL Selects the high speed oscillator or the low
RSVD
ITSEL2
ITSEL1
ITSEL0
ADCH3 ADC channel select bit
ADCH2 ADC channel select bit
ADCH1 ADC channel select bit
ADCH0 ADC channel select bit
ADMOD Places the ADC in single-ended or differential
MUX
PSC
ADBSY Signifies that the ADC is currently busy perform-
HSON
Channel Select
mode.
Enables the ADC multiplexor output.
Switches the ADC clock between a divide by one
or a divide by sixteen of MCLK.
ing a conversion. When set by the user, starts a
conversion.
Turns the low speed oscillator on or off.
Turns the high speed oscillator on or off.
Selects the high speed oscillator or the low
speed oscillator as the Idle Timer Clock.
speed oscillator as the primary CPU clock.
This bit is reserved and must be 0.
Idle Timer period select bit.
Idle Timer period select bit.
Idle Timer period select bit.
ADCH1
DCEN
ADCH0
CCKS
EL
ADMOD
RSVD
Select
Mode
Mux Out Prescale
ITSEL2
MUX
ITSEL1
PSC
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ADBSY
ITSEL0
Busy
Bit 0
Bit 0