m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 130

• Manufacturer Part Number: m30262f8gp
• Description: Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Clock Synchronous Serial I/O Mode
124
Figure 1.15.12. Typical transmit/receive timings in clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
RTSi
CLKi
RxDi
Receive complete
flag (Rl)
Receive interrupt
request bit (IR)
• Example of receive timing (when external clock is selected)
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CTSi
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
Transmit interrupt
request bit (IR)
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
Preliminary Specifications Rev. 0.9
The above timing applies to the following settings:
f
The above timing applies to the following settings:
EXT
Specifications in this manual are tentative and subject to change.
* Internal clock is selected.
* CTS function is selected .
* CLK polarity select bit = 0 .
* Transmit interrupt cause select bit = 0 .
* External clock is selected .
* RTS function is selected .
* CLK polarity select bit = 0 .
: frequency of external clock
H
1
0
1
0
1
0
1
0
1
0
L
H
1
0
1
0
L
1
0
1
0
Transferred from UARTi receive register
Data is set in UARTi transmit buffer register
Cleared to 0 when interrupt request is accepted, or cleared by software
to UARTi receive buffer register
D
Transferred from UARTi transmit buffer register to UARTi transmit register
Dummy data is set in UARTi transmit buffer register
0
D
0
D
1
D
1
D
T
D
2
CLK
2
D
D
3
3
Transferred from UARTi transmit buffer register to UARTi transmit register
Renesas Technology Corp.
D
D
4
1 / f
Tc
4
Receive data is taken in
D
D
5
5
Cleared to 0 when interrupt request is accepted, or cleared by software
EXT
D
D
6
6
D
D
7
7
Stopped pulsing because CTS = H
Read out from UARTi receive buffer register
D
D
0
Tc = TCLK = 2(n + 1) / fi
0
Even if the reception is completed, RTS do not assert,
and it is asserted by readout of receive buffer register.
D
1
D
fi: frequency of BRGi count source (f
n: value set to BRGi
1
Meet the following conditions are met when the CLK
input before data reception = H
D
2
D
* Transmit enable bit
* Receive enable bit
* Dummy data write to UARTi transmit buffer register
2
D
3
D
D
3
4
D
D
4
5
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
5
6
D
7
Stopped pulsing because transfer enable bit = 0
1
1
D
0
1
D
, f
1
8
, f
D
2
32
)
D
3
M16C/26 Group
D
4
D
5
D
6
D
7