r5f36406cnfa Renesas Electronics Corporation., r5f36406cnfa Datasheet - Page 68

• Manufacturer Part Number: r5f36406cnfa
• Description: M16c/64c Group Renesas Mcu
• Manufacturer: Renesas Electronics Corporation.

M16C/64C Group
R01DS0016EJ0100 Rev.1.00
Feb 07, 2011
Switching Characteristics
(V
Table 5.37
Notes:
CC1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-ALE)
h(BCLK-ALE)
d(AD-ALE)
h(AD-ALE)
d(AD-RD)
d(AD-WR)
dz(RD-AD)
5.2.4.3
1.
2.
3.
4.
5.
6.
= V CC2 = 5 V, V
Symbol
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
When using multiplex bus, set f
Calculated according to the BCLK frequency as follows:
0.5 10
--------------------- - 10 ns
(
----------------------------------- - 40 ns
0.5 10
--------------------- - 25 ns
0.5 10
--------------------- - 15 ns
f
f
f
n 0.5
(
(
(
BCLK
BCLK
BCLK
–
f
×
×
×
(
BCLK
)
)
)
) 10
9
9
9
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus)
×
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of address
WR signal output delay from the end of address
Address output floating start time
–
–
–
)
9
[
[
[
–
SS
]
]
]
= 0 V, at T
[
]
n is 2 for 2-wait setting, 3 for 3-wait setting.
(BCLK)
opr
Parameter
= -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified)
12.5 MHz or less.
0.5 10
--------------------- - 20 ns
f
(
BCLK
×
)
9
–
[
]
Figure 5.14
Measuring
Condition
See
(5)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 6)
(Note 3)
(Note 4)
Min.
5. Electrical Characteristics
− 4
0
0
0
0
0
0
Standard
V
CC1
Max.
= V
25
25
25
25
40
15
8
Page 68 of 88
CC2
= 5 V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns