tc90a67f TOSHIBA Semiconductor CORPORATION, tc90a67f Datasheet
tc90a67f
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tc90a67f Summary of contents
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... Single Chip Picture-in-Picture IC (PAL/NTSC) TC90A67F is a Picture-in-Picture (PIP) IC including a PIP controller and a PAL/NTSC decoder function on a chip. TC90A67F has an ADC, a video decoder, a vertical filter, a field memory, DACs and so on, so that it is easy to design a PIP application with the least external components. ...
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NC CKILL VCHIP RESET DD V SDA SCL NC PIPEN YS NC VSS PVD REF PH CKPSEL CKP SS V PHD NC TESTM0 TESTM1 TESTM2 CLMP CKCSEL CKC CKIN DD AV FILTER SS AV ...
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... Field odd/even output (main picture) 38 CFIELD O Field odd/even output (sub picture Vertical sync. output (sub picture) REF Horizontal sync. output (sub picture) REF ¾ Function 4 TC90A67F Condition normal: 2.3 V normal: 1.0 V normal: 1 internal, H: external normal even, L: odd H: even, L: odd 2002-02-06 ...
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... ROUT O Analog signal output (R ¾ Power supply for DAC DD 80 YOUT O Analog signal output ( Function 5 TC90A67F Condition H: color killer ON, L: OFF 23rd-line reset normal: H sub-picture: high normal: negative L: 24 MHz MHz normal: positive normal: H normal: H normal: H normal: H normal: 1 ...
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... System Block Diagram Main Video Sub Video PIP Mode Main V/C/J Chroma RGB Text Demo Processor Sync Processor Processor H/V YUV YUV PIP Controller Ys Sub V/C/J TC90A67F 6 TC90A67F YUV 1 PIP MODE Size: 1/3, 1/4, 1/6 6 PIP MODE 1 Size: 1/6 ´ PIP MODE 2 Size: 1/6 ´ 6 2002-02-06 ...
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... Function TC90A67F has horizontal and vertical sync separation circuit for sub picture, color demodulation circuit for sub picture, horizontal and vertical timing generation circuit for main picture, PIP control circuit. Color demodulation circuit consists of digital circuit, and corresponds to M-NTSC, PAL, M-PAL, N-PAL system possible to process the sub picture easily, according to adopting system clock of 24 MHz by digital PLL circuit locked fH ...
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... PVWN (sub address 12hex) or PVWP (sub address 13hex). PVWN: Vertical frequency of sub picture PVWP: Vertical frequency of sub picture DACs for Y Signal and Color Difference Signal TC90A67F is built-in three 8 bit-DAC in motion on 24 MHz. Output dynamic range is determined by the difference between V and ...
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... RGB or R-Y, Y, B-Y respectively by FRAMEYG, FRAMER, FRAMEB. (FRAMEW, FRAMEYG, FRAMER, FRAMEB: sub address 1Ehex) 13. CCD Slice Circuit This IC has a CCD slice circuit, picks up CCD data, the CCD data and CCD slice conditions can be checked on using IIC BUS read mode. 9 TC90A67F 2002-02-06 ...
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... Control internal Y-level. 000 Sub-pictures range in the main-picture. (horizontal width, fine) Sub-pictures range in the main-picture (vertical height) 001011 100 12 TC90A67F Comment 0: auto, 1: fix 0: hi-band, 1: low-band 0: hi-band, 1: low-band 00: 0, 01: 1/4, 10: 1/2, 11: 1 00: 1/3, 01: 1/4, 10: 1/5, 11: 1/6 00: 1/3, 01: 1/4, 10: 1/6, 11: 1/8 0: normal, 1: Fixed to single-field display 1110: strobe (once 58 fields) ...
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... Adjustment the demodulation phases for R-Y signal. (NTSC only) 000000: 0°, 111111: +45° Adjustment the demodulation phase for R-Y and B-Y signals. (NTSC only) 00 10000000: -45°, 00000000: 0°, 01111111: +45° 13 TC90A67F Comment , when main-picture system. (set the dividing number of fH PLL.) , when main-picture system system. ...
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... Reverse CFIELD at internal circuit. 0: normal, 1: reverse 1 Select output signal format. Set clock frequency of sub-picture processing system. 10 Set clock frequency of main-picture processing system TC90A67F Comment 0: auto, 1: fix 0: ON, 1: OFF 0: normal, 1: reverse 0: YUV, 1: RGB (set the dividing number of H-PLL) (set the dividing number of H-PLL) ...
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... N-PAL®M-PAL®M-NTSC, 11: FSSEL [1:0] Set slice level for CCD. (this data is initial value of peak detector circuit at auto-slice mode.) Set minimum-width of high-period in start-bit for CCD. Set minimum-width of low-period in start-bit for CCD. 15 TC90A67F Comment 0: Minimum level 63: maximum level 0: Minimum level 63: maximum level 3: 4 fields 2002-02-06 ...
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... Set polarity of horizontal sync pulse input at pin “PHD”. (main-picture Force 60 Hz mode (main-picture) 0 Force 50 Hz mode (main-picture) Fix to ‘0’ TC90A67F Comment 0: fix, 1: auto-slice 0: normal, 1: force 0: normal, 1: force 0: even high, 1: odd high 0: even high, 1: odd high 0: Negative, 1: Positive 0: Positive, 1: Negative ...
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... Slice level is fixed value of SSLV resistor. ON Renewed slice level reading value of SLV resistor only 2nd field. ON Renewed slice level reading value of SLV resistor only 1st field. 17 TC90A67F 1: 1st field, 0: 2nd field 0: not start-bit detected, 1: start-bit detected 0: OK, 1: too near 0: OK, 1: too near 0: exist, 1: not-signal ...
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... Output voltage Ambient temperature Symbol Rating + ± 1538 -55 to 125 T STG 70 100 125 Symbol Rating V 3 OUT DD - OPR 19 TC90A67F Unit °C Unit °C 2002-02-06 ...
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... AV DD ¾ ¾ BIASA ¾ ¾ V REFH ¾ ¾ V REFL ¾ ILE1 (8 bit precision) ¾ DLE1 (8 bit precision) ¾ ¾ DG ¾ ¾ TC90A67F Applicable Min Typ. Max Unit Terminals ¾ 160 230 mA ´ ¾ (Note1) DD 0.8 ´ ¾ ...
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... BIASD ¾ ¾ V REF ¾ ¾ ZOUT2 ¾ ¾ FCK1 ¾ ¾ VCK ¾ ¾ FCK2 ¾ ¾ FILTER 21 TC90A67F = = = = 3 25°C Applicable Min Typ. Max Unit Terminals ¾ ¾ 8 bit ¾ ¾ 1.5 V p-p ¾ ¾ 1.5 V p-p ¾ ¾ ...
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C21 NC CKILL CKILL VCHIP VCHIP RESET mF 0 C22 SDA SCL NC PIPEN PVD mF 0 C23 NC REF PH CKPSEL CKP SS V PHD NC TESTM0 TESTM1 TESTM2 ...
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... Package Dimensions Weight: 1.6 g (typ.) 23 TC90A67F 2002-02-06 ...
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... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 24 TC90A67F 000707EBA 2002-02-06 ...