ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 25

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

11. Configuring the Receiver
Table 11-3.
9248A–RKE–09/11
Bit 1
1
0
0
values of
Bit 3...14
values of
Bit 3...14
Default
Default
–
–
Bit 2
–
1
0
Effect of the Configuration Words within the Registers
Baud1
Bit 3
Lim_
min5
–
0
0
BR_Range
Baud0
Bit 4
Lim_
min4
–
0
1
The Atmel
registers called OPMODE and LIMIT. The registers can be programmed by means of the bidi-
rectional DATA port. If the register content has changed due to a voltage drop, this condition is
indicated by a the output pattern called reset marker (RM). If this occurs, the receiver must be
reprogrammed. After a Power-On Reset (POR), the registers are set to default mode. If the
receiver is operated in default mode, there is no need to program the registers.
page 25
the receiver is set back to polling mode using the OFF command (see
page
appropriate register to be programmed. For high programming reliability, bit 15 (Stop bit), at
the end of the programming operation, must be set to 0.
Table 11-1.
Table 11-2.
BitChk1
Bit 1
Bit 5
Lim_
min3
15) or whether it is programmed. Bit 2 represents the register address. It selects the
1
0
0
–
0
0
Lim_min
N
shows the structure of the registers. According to
Bit-check
Bit 15
®
ATA5723C/ATA5724C/ATA5728C receiver is configured using two 12-bit RAM
0
1
BitChk0
Bit 6
Lim_
min2
Effect of Bit 1 and Bit 2 on Programming the Registers
Effect of Bit 15 on Programming the Register
–
1
1
Bit 2
Atmel ATA5723C/ATA5724C/ATA5728C
x
1
0
Modu-
_FSK
lation
ASK/
Bit 7
Lim_
min1
–
0
0
OFF command
Action
The receiver is set back to polling mode (OFF command)
The OPMODE register is programmed
The LIMIT register is programmed
Action
The values are written into the register (OPMODE or LIMIT)
The values are not written into the register
OPMODE register
Sleep4
Bit 8
Lim_
min0
LIMIT register
–
0
1
Sleep3
max5
Bit 9
Lim_
–
0
1
Sleep2
Bit 10
max4
Lim_
Sleep
–
1
0
Sleep1
Bit 11
max3
Lim_
–
1
1
Lim_max
Table
Sleep0 X
Bit 12
max2
Lim_
–
0
0
11-1, bit 1 defines whether
Bit 13
X
max1
SleepStd
Lim_
Sleep
–
0
0
“Receiving Mode” on
Suppression
Disable
Noise_
Bit 14
Noise
max0
Lim_
Table 11-3 on
–
1
1
Bit 15
–
–
0
–
–
–
0
–
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