tc59lm913amg TOSHIBA Semiconductor CORPORATION, tc59lm913amg Datasheet - Page 32

• Manufacturer Part Number: tc59lm913amg
• Description: 512mbits Network Fcram1 Sstl_2 Interface ? 4,194,304-words ? 8 Banks ? 16-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Command
BA0~BA2
L/UDQS
A13~A0
(output)
(output)
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
CLK
CLK
DQ
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
RDA
UA
BA
0
Hi-Z
LAL
LA
1
2
CL + BL/2
3
DESL
4
5
Q0 Q1
RDA
6
(opcode)
BA0="0"
BA1="0"
BA2="0"
MRS
Valid
7
8
9
10
DESL
I
RSC
11
TC59LM913AMG-50
12
2005-11-08 32/46
13
WRA
RDA
UA
BA
14
or
Rev 1.1
LAL
LA
15