tc59lm818dmb TOSHIBA Semiconductor CORPORATION, tc59lm818dmb Datasheet - Page 47

• Manufacturer Part Number: tc59lm818dmb
• Description: 288mbits Network Fcram2 ? 4,194,304-words ? 4 Banks ? 18-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Unidirectional DS/QS mode
Unidirectional DS/QS mode
SELF-REFRESH ENTRY TIMING
Command
SELF-REFRESH EXIT TIMING
Command
(output)
(output)
(output)
(output)
CLK
CLK
CLK
CLK
DQ
DQ
PD
QS
PD
QS
Notes: 1.
Notes: 1.
I
RCD
Qx
*2
t
WRA
QPDH
t
Self-Refresh Exit
= 1 cycle
FPDL (min)
0
0
2.
3. It is desirable that clock input is continued at least l
4. In case of Self-Refresh entry after Write Operation, from the LAL command following WRA to the
Hi-Z
Hi-Z
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I
4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
5. Any command (except Read command) can be issued after I
6. Read command (RDA + LAL) can be issued after I
Low
Refresh mode.When PD is brought to "Low" after l
and enter Power down mode. In case of PD fall between t
will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be
specified which mode TC59LM818DMB operates.
brought to “Low” for Self-Refresh Entry.
REF command delay time is Write latency(WL)+2 clock cycles minimum.
other operation.
PD must be brought to "Low" within the timing between t
DESL
REF
t
1
1
PDEX
is don’t care.
is don’t care.
t
FPDL (max)
*3
Hi-Z
I
REFC
2
2
WRA
m − 1
3
Self Refresh Entry
I
*4
RCD
I
REFC
Auto Refresh
REF
= 1 cycle
m
4
I
*4
PDV
I
CKD
DESL
m + 1
*2
5
I
LOCK
I
REFC
DESL
REFC
m − 1
m + 2
after PD is brought to “High”.
LOCK
CKD
PDV
, TC59LM818DMB perform Auto Refresh
from REF command even though PD is
.
n − 1
FPDL
m
FPDL
I
REFC
RCD
(min) and t
(max) and l
TC59LM818DMB-33,-40
m + 1
Command (1st)
= 1 cycle
.
n
Command (2nd)
FPDL
n + 1
PDV
(max) to Self
2005-10-19 47/57
, TC59LM818DMB
Hi-Z
*5
RDA
p − 1
*6
*5
Low
LAL
Rev 1.4
p
*6