tc59lm836dkg TOSHIBA Semiconductor CORPORATION, tc59lm836dkg Datasheet - Page 54

• Manufacturer Part Number: tc59lm836dkg
• Description: 288mbits Network Fcram2 ? 2,097,152-words ? 4 Banks ? 36-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

COMMAND FUNCTIONS and OPERATIONS
mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
TC59LM836DKB are introduced the two consecutive command input method. Therefore, except for Power Down
Read Operation (1st command + 2nd command = RDA + LAL)
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the
next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing
of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after l
Write Operation (1st command + 2nd command = WRA + LAL)
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS
input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input
after CAS latency-1 from the issuing of the LAL command. The DS has to be provided for a burst length. The
back automatically to the idle state after l
LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF
command having gone into the next clock of the WRA command instead of the LAL command. The minimum
period between the Auto-Refresh command and the next command is specified by l
synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh,
Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh
or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands has to be more
than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within 3.2 µs (8 ×
400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM836DKB become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for l
it is desirable that clock input is kept in l
“Low”. During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks
specified by l
Auto-Refresh command is issued to avoid the violation of the refresh period just after l
exit.
Power Down Mode (
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation
lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be
issued for l
CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
TC59LM836DKB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM836DKB become Power
PDA
REFC
cycle after PD goes high. The Power Down exit function is asynchronous operation.
. The Self-Refresh exit function is asynchronous operation. It is required that one
PD
= “L”)
RC
.
CKD
RC
. Write Burst Length is controlled by VW0 and VW1 inputs with
period. The device is in Self-Refresh mode as long as PD held
TC59LM836DKG-33,-40
REFC
REFC
2005-11-08 54/65
PD
REFC
. However, about a
period. In addition,
= “L”)
from Self-Refresh
FPDL
Rev 1.4
from the