tc59lm814 TOSHIBA Semiconductor CORPORATION, tc59lm814 Datasheet - Page 30

• Manufacturer Part Number: tc59lm814
• Description: 256mbits Network Fcram1
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Command
Command
SELF-REFRESH ENTRY TIMING (CL = 3)
SELF-REFRESH EXIT TIMING
(output)
(output)
(output)
(output)
DQS
DQS
CLK
CLK
CLK
CLK
DQ
DQ
PD
PD
Notes: 1. “×” is don’t care.
Notes: 1. “×” is don’t care.
Qx
*2
t
t
WRA
FPDL (min)
QPDH
×
Self-Refresh Exit
I
RCD
0
0
*1
2.
3. It is necessary that clock input is continued at least 16 clock cycles from REF command even
Hi-Z
Hi-Z
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I
4. I
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
6. Any command (except Read command) can be issued after I
7. Read command (RDA + LAL) can be issued after I
= 1 cycle
Refresh mode.When PD is brought to "Low" after l
enter Power down mode.
though PD is brought to “Low” for Self-Refresh Entry.
other operation.
PD must be brought to "Low" within the timing between t
PDA
I
PDA
REF
1
1
is defined from the first clock rising edge after PD is brought to “High”.
DESL
t
t
= 1 cycle
PDEX
FPDL (max)
Hi-Z
Hi-Z
I
REFC
*3
2
2
*4
WRA
Self Refresh Entry
m − 1
I
RCD
Auto Refresh
3
I
CKD
*5
= 1 cycle
I
I
REFC
PDV
REF
= 16 cycles
m
4
*2
*5
DESL
m + 1
5
*3
I
I
REFC
LOCK
DESL
REFC
m − 1
m + 2
after PD is brought to “High”.
LOCK
PDV
, FCRAM
.
I
n − 1
RCD
FPDL
m
TC59LM814/06CTG-50,-60
REFC
= 1 cycle
(min) and t
TM
Command (1st)
m + 1
.
n
perform Auto Refresh and
Command (2nd)
FPDL
n + 1
(max) to Self
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×
*6
*1
RDA
p − 1
*7
*6
LAL
p
Rev 1.2
*7