xrt81l27 Exar Corporation, xrt81l27 Datasheet
xrt81l27
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xrt81l27 Summary of contents
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... SDH multiplexers that accommodate TU12 Tributary Unit Frames. Line cards in these units multiplex 21 E1 channels into higher SDH rates. Devices with seven E1 interfaces such as the XRT81L27 provide the most efficient method of implementing 21-channel line cards. Each channel performs the driver and re- ceiver functions necessary to convert bipolar signals to logical levels and vice versa ...
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... TPOS_0/TDATA_0 120 TClk_0 121 GND 122 VDD 123 RPOS_2/RDATA_2 124 RNEG_2/LCV_2 125 RClk_2 126 LOS_2 127 RPOS_0/RDATA_0 128 RNEG_0/LCV_0 P N ART UMBER XRT81L27IV XRT81L27 ORDERING INFORMATION P ACKAGE 128 Lead TQFP 2 RClk_6 64 63 RNEG_6/LCV_6 62 RPOS_6/RDATA_6 61 LOS_6 60 RClk_5 59 RNEG_5/LCV_5 58 RPOS_5/RATA_5 57 LOS_5 56 VDD GND ...
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... SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY GENERAL DESCRIPTION .................................................................................................. 1 F ................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS Figure 1. Block Diagram ................................................................................................................... 1 Figure 2. Pin Out of the XRT81L27 ................................................................................................... 2 ORDERING INFORMATION ............................................................................................................... 2 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTIONS ........................................................................................................... ABLE IN UMBER BY ELECTRICAL CHARACTERISTICS ................................................................................. 10 ...
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... HE INE RIVER BLOCK 2 NTERFACING THE RANSMIT Figure 12. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for 75 or 120W Applications) ................................................................................................... 23 3.0 The Receive Section ............................................................................................................................... 23 3 NTERFACING THE ECEIVE Figure 13. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W (Transformer-Coupled) Applications ...
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... Analog Supply Ground. I Receiver 4 Bipolar Positive Input: I Receiver 4 Bipolar Negative Input: Power-down Transmitter 4: (see pin 6) O Transmitter 4 Tip Output: Positive bipolar data output to the line. Transmitter 4 Positive Supply(3.3V± 5%) O Transmitter 4 Ring Output: Negative bipolar data output to the line. 3 XRT81L27 REV. 1.1.0 D ESCRIPTION ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1.0 PIN DESCRIPTIONS indicates an input pin with a 50k pull-up Resistor, I-L indicates an input pin with a 50k pull-down resistor. OTE AME 26 TGND_4 Gnd 27 PDTx_6 I-H 28 TTIP_6 29 TVDD_6 Vdd 30 TRING_6 31 TGND_6 Gnd 32 MODE ...
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... Host Mode, this pin must be asserted "Low" in order to enable commu- nication with the device via the Serial Interface. Hardware Mode, B3, together with B1 and B2 are control bits to select which of the seven channels to be placed in Loop-back mode. (see pin 48 description) I-L Transmit All Ones Channel_5: (see pin 40) 5 XRT81L27 REV. 1.1.0 D ESCRIPTION B2 B3 Chan ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1.0 PIN DESCRIPTIONS indicates an input pin with a 50k pull-up Resistor, I-L indicates an input pin with a 50k pull-down resistor. OTE AME 52 TNEG_5/ CODE_5 53 TPOS_5/ TDATA_5 54 TClk_5 55 GND Gnd 56 VDD Vdd 57 LOS_5 ...
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... Receiver 1 Loss of Signal: (see pin 2) O Receiver 1 Clock Output: O Receiver 1 Negative Data Output: (see pin 34) O Receiver 1 Positive/NRZ Data Output: (see pin 35) O Receiver 3 Loss of Signal: (see pin 2) O Receiver 3 Clock Output: O Receiver 3 Negative Data Output: (see pin 34) 7 XRT81L27 REV. 1.1.0 D ESCRIPTION ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1.0 PIN DESCRIPTIONS indicates an input pin with a 50k pull-up Resistor, I-L indicates an input pin with a 50k pull-down resistor. OTE AME 102 RPOS_3/ RDATA_3 103 AVDD AVdd 104 AGND Gnd 105 ...
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... SClk 49 9 XRT81L27 REV. 1.1.0 D ESCRIPTION AME TPOS TNEG PDT TAOS TV DD 119 118 6 117 8 106 107 91 108 89 115 114 11 113 13 110 111 86 112 84 38 ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1.0 ELECTRICAL CHARACTERISTICS S T TORAGE EMPERATURE O T PERATING ESD UPPLY T HETA T HETA a. Human Body Model b. mounted on 4 (or more) layer board c. mounted on 3 (or less) layer board T P ARAMETER Input High Voltage Input Low Voltage ...
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... UIpp 0.3 ---- 0 ---- dB 20 ---- dB 16 ---- dB 11 XRT81L27 REV. 1.1.0 , TRANSMISSION AND RECEIVE C ONDITIONS T C EST ONDITIONS Cable attenuation @1024KHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. With 6dB cable loss. Between RTIP or RRING to ground ITU G ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1 IGURE ECEIVE UTPUT IMING RClk RClkP=0 RPOS/RNEG RClkP=1 RPOS/RNEG IGURE RANSMIT NPUT IMING TClk TClkP=0 TPOS/TNEG TClkP=1 TPOS/TNEG T SU (VDD=3. ARAMETER TCLK Clock Period TCLK Duty Cycle ...
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... M S ICROPROCESSOR ERIAL . TION The XRT81L27 MSI uses a simple four wire interface that is compatible with most microcontrollers. Either hardware blocks in the micro can supply the data or “bit-banging” can be used. This interface consists of the following signals: CS (pin 50) Chip Select (Active Low) ...
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... SCLK after CS has been asserted. This bit indicates whether the current operation is a Read or Write operation. A “1” in this bit specifies a Read from the XRT81L27, a “0” in this bit specifies a Write to the device. Bits 2 through 5: The four (4) bit Address Values ...
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... R/W = “0” for “Write” Operations ERIAL NTERFACE P ARAMETER NTERFACE ATA TRUCTURE XRT81L27 REV. 1.1 IMING SEE IGURE NITS 240 ns 240 ns 500 250 ns 200 ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1.0 1.2 Description of the Command Registers A listing of these Command Registers, their binary/ hex Addresses and their Bit-Formats are in Table 9. All bits are reset to zero by activation of the Reset sig- nal (RST, pin 3). All other registers (0111 through ...
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... BACK EGISTERS DDRESS F UNCTION OOP BACK EGISTERS DDRESS F UNCTION - A : 0100, HEX 0 EGISTERS DDRESS F UNCTION - A : 0101, HEX 0 EGISTERS DDRESS F UNCTION 17 XRT81L27 REV. 1.1.0 : 0001, HEX EGISTER YPE R/W : 0010, HEX EGISTER YPE R/W : 0011, HEX EGISTER YPE R ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REV. 1.1.0 T 16: PDT ABLE AME 0-6 PDTx0- Power-down Transmitter: PDTx6 Writing a "1" to this bit shut down the transmitter channel selected and places the TTIP/TRing driver in high impedance mode. Individual pin control is also available to switch off the transmitter for fast redundancy application both in Host and Hardware mode ...
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... TxNEG TxClk positive polarity pulse via the TTIP and TRING output pins. If the XRT81L27 samples a “1” on the TNEG in- put pin, the Transmit Section of the device generates a negative polarity pulse via the TTIP and TRING out- put pins. HDB3 Encoding will already have been done on this data ...
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... Remote loop- back provides a path for the XRT81L27 to send re- ceived data back over the Transmit line (TTIP - TRING) to the “other” end of the Timing Control block ...
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... E1 applications, even with TClk duty cycle be- tween 30 and 70 consequence, each channel (within the XRT81L27) will take each mark which is provided to it via the Transmit Input Interface block, and will gener- ate a pulse that complies with the pulse template, presented in Figure 11, (when measured on the sec- ondary-side of the Transmit Output Transformer) ...
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... Note – V corresponds to the nominal peak value. 2.6 I NTERFACING THE XRT81L27 In both (75 or 120 ) applications, the user is ad- vised to interface the Transmitter to the Line, using the termination as shown in Figure 12. This includes 1:2 transformer with the intrinsic impedance of the line used as a termination resistance. ...
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... E1 specify 75 termination loads, when transmitting over coaxial cable, and 120 ting over twisted-pair. Figure 13, Figure 14 and Figure 15 present the various methods that can be employ to interface the Receivers (of the XRT81L27) to the line. The receive circuits of Figure 13, Figure 14 and Figure 15 differ in the impedance at the ECTIONS TO THE inputs and the line connections ...
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... RPOS_n RTIP_n RNEG_n RClk_n LOS_n RRING_n XRT81L27 R S ECEIVE ECTIONS OF THE RPOS_n RTIP_n RNEG_n RClk_n RRing_n LOS_n XRT81L27 ed: Pulse PE-65681, Pulse T1090, and HALO TG08- 1505N1. 24 XRT81L27 THE INE FOR Line Input 1: 2 XRT81L27 L 120 TO THE INE FOR 1:2 Line Input ...
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... B HE ECEIVE QUALIZER OCK After a given Channel (within the XRT81L27) has re- ceived the incoming line signal, via the RTIP_n (where _n is the channel number) and RRING_n in- put pins, the first block that this signal will pass through is the Receive Equalizer block. ...
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... In particular, the XRT81L27 will declare an LOS between 10 and 255 UI (or E1 bit periods) after the actual time the LOS condition occurred. Further, the XRT81L27 will clear the LOS indicator within 10 to 255 UI after restoration of the incoming line signal. When operating in the Host mode, the LOS time can be extended to 4096 zeros by the activation of the EXLOS bit in the Command Control Register ...
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... INCHES MILLIMETERS MIN MAX MIN 0.055 0.063 1.40 0.002 0.006 0.05 0.053 0.057 1.35 0.007 0.011 0.17 0.004 0.008 0.09 0.858 0.874 21.80 0.783 0.791 19.90 0.622 0.638 15.80 0.547 0.555 13.90 0.020 BSC 0.50 BSC 0.018 0.030 0. XRT81L27 REV. 1.1 MAX 1.60 0.15 1.45 0.27 0.20 22.20 20.10 16.20 14.10 0.75 7 ...
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... XRT81L27 SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY REVISIONS Rev. 1.0.1 changed package from 14x14mm 128 pins to 14x20mm 128 pins. Rev. 1.0.2 Added info on serial processor interface. Corrected pin out for pins 33, 34, 35, 36, 37, 38, 97, 98, 101 and 102. Rev. 1.0.3 Corrected typos in pin list (pin 29, 51, 64 and 118) and Pin out diagram (pins 47, 48 and 69). ...